Patents by Inventor Jackson Kong
Jackson Kong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10079158Abstract: An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.Type: GrantFiled: December 12, 2014Date of Patent: September 18, 2018Assignee: INTEL CORPORATIONInventors: Jackson Kong, Bok Eng Cheah, Khang Choong Yong, Howard L. Heck, Kuan-Yu Chen
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Patent number: 10041282Abstract: A personal computing device is provided with a first housing portion, a second housing portion, and a hinge joining the first housing portion to the second housing portion. The hinge is configured to allow the first housing portion to rotate substantially three-hundred-sixty degrees relative to the second housing portion. The hinge can be implemented as a plurality of interlinked parallel hinge segments, each hinge segment to rotate about a respective one of a plurality of parallel axes of the hinge to enable the rotation of the first housing portion.Type: GrantFiled: December 24, 2015Date of Patent: August 7, 2018Assignee: Intel CorporationInventors: Bok Eng Cheah, Howe Yin Loo, Min Suet Lim, Chung Peng Jackson Kong, Poh Tat Oh
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Patent number: 10036187Abstract: An apparatus is provided including a docking device to accept a computing device, the docking device including a keyboard and a hinge to connect the computing device to the keyboard, the hinge is configured to allow the computing device, when connected to the hinge, to rotate relative to the keyboard in a laptop orientation. The hinge includes a plurality of interlinked parallel hinge segments at least partially enclosed in a flexible covering, and each hinge segment is to rotate about a respective one of a plurality of parallel axes of the hinge.Type: GrantFiled: January 15, 2016Date of Patent: July 31, 2018Assignee: Intel CorporationInventors: Bok Eng Cheah, Howe Yin Loo, Min Suet Lim, Chung Peng Jackson Kong, Poh Tat Oh
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Patent number: 10000954Abstract: A personal computing device is provided with a first housing portion, a second housing portion, and a hinge joining the first housing portion to the second housing portion. The hinge is configured to allow the first housing portion to rotate substantially three-hundred-sixty degrees relative to the second housing portion. The hinge can be implemented as a plurality of interlinked parallel hinge segments, each hinge segment to rotate about a respective one of a plurality of parallel axes of the hinge to enable the rotation of the first housing portion.Type: GrantFiled: December 24, 2015Date of Patent: June 19, 2018Assignee: Intel CorporationInventors: Bok Eng Cheah, Howe Yin Loo, Min Suet Lim, Chung Peng Jackson Kong, Poh Tat Oh
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Patent number: 10000953Abstract: An apparatus is provided including a docking device to accept a computing device, the docking device including a keyboard and a hinge to connect the computing device to the keyboard, the hinge is configured to allow the computing device, when connected to the hinge, to rotate relative to the keyboard in a laptop orientation. The hinge includes a plurality of interlinked parallel hinge segments at least partially enclosed in a flexible covering, and each hinge segment is to rotate about a respective one of a plurality of parallel axes of the hinge.Type: GrantFiled: January 15, 2016Date of Patent: June 19, 2018Assignee: Intel CorporationInventors: Bok Eng Cheah, Howe Yin Loo, Min Suet Lim, Chung Peng Jackson Kong, Poh Tat Oh
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Patent number: 9543244Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.Type: GrantFiled: November 17, 2014Date of Patent: January 10, 2017Assignee: Intel CorporationInventors: Chung Peng Jackson Kong, Chang-Tsung Fu, Telesphor Kamgaing, Chan Kim Lee, Ping Ping Ooi
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Publication number: 20160174374Abstract: An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.Type: ApplicationFiled: December 12, 2014Publication date: June 16, 2016Inventors: Jackson Kong, Bok Eng Cheah, Khang Choong Yong, Howard L. Heck, Kuan-Yu Chen
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Publication number: 20150069629Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.Type: ApplicationFiled: November 17, 2014Publication date: March 12, 2015Inventors: Chung Peng Jackson KONG, Chang-Tsung Fu, Telesphor Kamgaing, Chan Kim Lee, Ping Ping Ooi
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Patent number: 8890302Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.Type: GrantFiled: June 29, 2012Date of Patent: November 18, 2014Assignee: Intel CorporationInventors: Chung Peng (Jackson) Kong, Chang-Tsung Fu, Telesphor Kamgaing, Chan Kim Lee, Ping Ping Ooi
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Publication number: 20140001643Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Inventors: Chung Peng (Jackson) KONG, Chang-Tsung FU, Telesphor KAMGAING, Chan Kim LEE, Ping Ping OOI