Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more command signals, a read data path control signal and one or more write data path control signals in response to an integrity protection control signal and one or more arbitration signals. The second circuit may be configured to write data to a memory and read data from the memory in response to the one or more command signals, the read data path control signal and the one or more write data path control signals. In a first mode, the data may be written and read without integrity protection. In a second mode the data may be written and read with integrity protection, and the integrity protection is written and read separately from the data.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more command signals, a read data path control signal and one or more write data path control signals in response to an integrity protection control signal and one or more arbitration signals. The second circuit may be configured to write data to a memory and read data from the memory in response to the one or more command signals, the read data path control signal and the one or more write data path control signals. In a first mode, the data may be written and read without integrity protection. In a second mode the data may be written and read with integrity protection, and the integrity protection is written and read separately from the data.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: A clock divider circuit and methods of operating same includes a standard integral clock divider circuit and a phase slip non-integral divider circuit for high granularity non-integral clock division. A multi-phase frequency synthesizer produces a plurality of phases of a clock frequency and applies the multiple phases to the divider circuit of the present invention. In a first embodiment, each phase is applied to a phase slip divider circuit which includes a integral divider portion and a programmable phase slip divider portion which receives the output of the integral division portion. Each phase of the input clock may therefore be divided by a wide variety of integral and non-integral divisors. In a second, simpler embodiment, a multi-phase frequency synthesizer produces a plurality of phases and applies the phases to a single phase slip divider.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: In a storage target device controller capable of managing multiple command contexts, methods and associated apparatus are provided for automatically managing the plurality of contexts using a state machine model. The state machine model is operable on a target device controller having an active context register set for processing of the presently active transfer on the host channel and an inactive context register set for storing an inactive context. The active context register set and inactive context register set are rapidly and automatically swapped by operation of the state machine model to resume or start processing of an inactive context. Additional inactive contexts are stored in a buffer memory associated with the target device controller. The inactive context register set is automatically stored into a selected one of the additional inactive contexts or loaded from a selected one of the additional inactive contexts by operation of the state machine model of the present invention.

Abstract: In a storage target device controller capable of managing multiple command contexts, methods and associated apparatus are provided for enabling simultaneous, independent operation of the disk channel and the host channel. In a multi-context target device controller, an active context initiates a requested exchange of data blocks between the host channel and the disk channel of the target device. The controller may swap the active context with an inactive context to better utilize resources of the target device such as the host channel bandwidth. The present invention provides for continued independent operation of the host channel and the disk channel. Counters associated with the active context are only updated by operation of the disk channel if the active context is the initiating context of the disk operations.

Abstract: In a data processing system having few initiators or several initiators with the same parameters, support for all initiators is provided by storing sets of parameters and corresponding lists of initiator IDs in cache entries. Based on the initiator ID in a selection command, the target selects the appropriate parameters and automatically transitions to data transfer mode. Low cost support for all initiators is thus provided.

Abstract: A storage target device controller (such as an embedded controller in a SCSI disk drive) processes multiple commands concurrently in accordance with the methods and structures of the present invention. Each command is stored within its own context within the target device controller to retain all unique parameters required for the processing of each command. Processing of multiple commands permits switching of command contexts within the target device to improve utilization of resources associated with the target device. For example, when a first, active, command context is prevented from further processing due to the status of the disk channel, an inactive command context may be swapped with the active command context to better utilize the host channel communication bandwidth. Similarly, a first active command context may be configured to automatically switch to a linked command context upon completion of processing to further ease management of multiple contexts.

Abstract: A method and apparatus for writing data to a storage device such as a hard disk drive in which two write commands from an initiator are processed as a single command at the storage device. A first request is received from a small computer systems interface (SCSI) bus to write a first set of data to a storage device. The first set of data is transferred to memory for temporary storage prior to transfer to the storage device. Thereafter, a second write request is received to write a second set of data to the storage device in which the write request includes a logical block address. An ending logical block address determined after transferring the first set of data is compared to the logical block address of the second request to determine whether the second set of data can be written to the storage device along with the first set of data as a single write operation based on the comparison of the logical block address of the second request and the ending logical block address.

Abstract: In a SCSI controller, unexpected messages are automatically received in response to an attention signal by receiving all of the bytes constituting the message and storing those bytes in an available register file selected from a plurality of register files in the controller. Once the entire message has been received and stored, a determination of an appropriate response is initiated. The register files are also used to hold selection information during a bus-initiated selection, so additional architecture is not required.

Abstract: A computer memory system connectable to a processor and having programmable operational characteristics based on characteristics of the processor. The memory system includes several caches and a main memory connected to a bus. One cache can be programmed to store only code data. Another cache can be programmed to buffer data writes to the main memory only from the processor. The main memory supports fast page mode and can be programmed to selectively reopen either code or non-code data pages.

Abstract: A serial data interface device is coupled to electronic devices or other data transmitters or receivers, such as disk, optical, tape or CD-ROM drives, computers, printers, etc. The interface includes first and second ports capable of receiving and transmitting information to respective electronic devices, and first and second storage devices, such as frame buffers, for storing information. Each of the storage devices is coupled to both the first and second ports and are coupled to another electronic device. Included in each storage device is a main memory that is coupled to at least one of the electronic devices and at least one of the ports. A control memory that is coupled to the main memory is also included, along with a main memory arbiter that is coupled to the control memory and the main memory. Further included is a buffer allocation control that is coupled to the at least one electronic device and at least one of the ports.

Abstract: A statistically fast, high performance computer memory system including a system memory for storing code and non-code data accessible by at least two bus masters, a bus connecting the memory with the bus masters, and a plurality of caches connected to the bus. An internal cache holds data selected solely on the basis of memory accesses by the host processor, a pre-fetch cache pre-fetches code from the memory, and a write buffer cache connected to the bus for buffering data written to the memory.

Abstract: A method for reading data from an n-way, set associative cache. n individually addressable memory units are provided, with each of the units storing a plurality of data elements. All n of the units are concurrently addressed to transfer a data element from each of the units to a respective latch, and one of such data elements is selectively transferred from one of the latches. The units are then serially addressed in a predetermined pattern to sequentially transfer data elements out of the units.

Abstract: A method for reading a multiple byte data element stored in both first and second memories. Selected bytes of the data element are invalidated in the first memory. Valid bytes from the first memory are combined with remaining bytes from the second memory in response to a read request.