Patents by Inventor Jackson Leung

Jackson Leung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Current controlled multi-state parallel test for semiconductor device
    Patent number: 6615391
    Abstract: A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a gate control circuit (312). The gate control circuit (312) provides either a first logic value, a second logic value, or an intermediate logic value to an open drain output driver (314) depending upon the test result data values (PASS and DATA_TST). In response to the logic values received from the gate control circuit (312), the open drain output driver (314) drives a data output (DQ) to a first, second or intermediate logic level.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: September 2, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Brian L. Brown, Jackson Leung, Ronald J. Syzdek, Pow Cheah Chang
  • Current controlled multi-state parallel test for semiconductor device
    Publication number: 20020080668
    Abstract: A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a gate control circuit (312). The gate control circuit (312) provides either a first logic value, a second logic value, or an intermediate logic value to an open drain output driver (314) depending upon the test result data values (PASS and DATA_TST). In response to the logic values received from the gate control circuit (312), the open drain output driver (314) drives a data output (DQ) to a first, second or intermediate logic level.
    Type: Application
    Filed: March 1, 2002
    Publication date: June 27, 2002
    Inventors: Brian L. Brown, Jackson Leung, Ronald J. Syzdek, Pow Cheah Chang
  • Two pass multi-state parallel test for semiconductor device
    Patent number: 6408411
    Abstract: A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path receives parallel I/O line (I/O0-I/O7) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a two-bit register (312) and output in a sequential fashion to an open drain output driver (314). In this manner, test result data values are provided by driving an output (DQ) in a rapid sequential fashion, rather than placing the output at one of three states (such as logic high state, a logic low state, or a high impedance state).
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: June 18, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Brian L. Brown, Jackson Leung, Ronald J. Syzdek, Pow Cheah Chang
  • Current controlled multi-state parallel test for semiconductor device
    Patent number: 6381718
    Abstract: A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a gate control circuit (312). The gate control circuit (312) provides either a first logic value, a second logic value, or an intermediate logic value to an open drain output driver (314) depending upon the test result data values (PASS and DATA_TST). In response to the logic values received from the gate control circuit (312), the open drain output driver (314) drives a data output (DQ) to a first, second or intermediate logic level.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: April 30, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Brian L. Brown, Jackson Leung, Ronald J. Syzdek, Pow Cheah Chang