Abstract: A mechanism is provided for removal of instructions for context re-evaluation. The mechanism receives an external request to perform the instruction remove. In response to this external request, the mechanism next determines when the state of the system is stable for allowing the instruction remove. Then the mechanism creates a first event to remove a current data instruction in a DMA, if present, and merge it back onto the list of pending contexts from where it originated. The mechanism waits for feedback that the first event has completed. Then the mechanism creates a second event to remove a pending data instruction that was chosen to be next in the DMA, if present, and merge it back onto the list of pending contexts from where it originated. Finally the mechanism waits for feedback that the second event has completed.

Abstract: Method and system for dividing a data segment of unknown length into first and second halves, for example, for interleaving the first and second halves. Units of the data segment are written into first and second register files. With respect to the first register file, responsive to determining that the last unit of the data segment has been written into the first register file, units of the data segment in the first register file that are not units of the first half of the data segment are removed, wherein the first register file stores the first half of the data segment.

Abstract: A configurable buffer arbiter is provided that combines a time-slot based algorithm, a fairness-based algorithm, and a priority-based algorithm to meet the bandwidth and latency requirements of multiple channels needing access to a buffer memory. The channels have different static and dynamic characteristics. The static channel characteristics include aspects such as a required latency for access to the buffer memory, a required bandwidth to the buffer memory, a preferred latency or bandwidth to the buffer memory, the amount of data the channel can burst in each access to the buffer memory, and the ability for the channel to continuously burst its data to the buffer memory with or without any pauses. The dynamic characteristics include aspects such as whether a channel's FIFO is nearing full or empty, or whether one of the static characteristics has suddenly become more critical. Configuration of the arbiter algorithms exists to optimize the arbiter for both the static and dynamic channel characteristics.

Abstract: Skip logic is provided in a storage controller that informs a direct memory access (DMA) context list manager of consecutive ones and zeroes in a skip mask table. The DMA context list manager then manages data counters and location pointers based on the number of consecutive ones and the number of consecutive zeroes. For writes and non-cached reads, the number of zeroes is used to adjust a logical sector address without actually moving data. For cached reads, the number of zeroes is used to adjust the logical sector address and a host address pointer. The DMA context list manager also determines an instruction length based on a number of consecutive ones and issues one or more instructions for each group of consecutive ones and subtracts the instruction lengths from the overall transfer length until the transfer is complete.

Abstract: A flow-based FIFO sub-system for a disk formatter in a data processing system that performs data width conversion. The sub-system has a first FIFO unit having a first width interfacing to a first bursting channel, and a second FIFO unit having a second width interfacing to a second bursting channel, the second width not being a multiple of the first width and the first width not being a multiple of the second width. Data width conversion is performed between the first FIFO unit and the second FIFO unit to convert data moving from the first FIFO unit to the second FIFO unit from the first width to the second width, and to convert data moving from the second FIFO unit to the first FIFO unit from the second width to the first width. The sub-system also includes an Error Correcting Code interface between the first FIFO unit and the second FIFO unit for performing in-line correction.

Abstract: A method and apparatus in a data controller in a storage drive for retrieving, evaluating, and processing a context that describes a direct memory access (DMA) request. The data controller includes a buffer for storing data transferred in response to execution of a DMA transfer request, a host address pointer pointing to a current location in the buffer, and a retrieval channel device. The retrieval channel device is configured to: fetch a context that describes a DMA transfer requested by a host computer, determine whether a current capacity of the buffer for transferring data exceeds a threshold, generate an instruction to transfer a second amount of data to complete at least a portion of the requested DMA transfer if the current capacity does exceed the threshold, assert the instruction generated by the retrieval channel device, and adjust the host address pointer by the second amount of data.

Abstract: System, apparatus and method for controlling the movement of data in a data processing system. The apparatus receives commands from at least one protocol engine and generates contexts representing the commands. The contexts are a data structure representing information for programming data transfers pursuant to the commands. Instruction requests based on the contexts are issued to the at least one protocol engine and to at least one DMA to efficiently control the movement of data to/from the at least one protocol engine from/to a local memory. The functions within the system are partitioned in a way that allows functions to be scaled for better performance and/or to support different protocols.

Abstract: Method and system for dividing a data segment of unknown length into first and second halves, for example, for interleaving the first and second halves. Units of the data segment are written into first and second register files. With respect to the first register file, responsive to determining that the last unit of the data segment has been written into the first register file, units of the data segment in the first register file that are not units of the first half of the data segment are removed, wherein the first register file stores the first half of the data segment.