Abstract: Described herein are various technologies for metrics-based assessment and trust verification of netlists for hardware logic devices (e.g., ASICs, FPGAs, etc.). A computing system translates a netlist of a hardware logic device into a Boolean network. The computing system generates and assigns metrics to edges of the Boolean network. The metrics comprise a coverage metric, a rare trigger metric, and an influence metric. Based upon the metrics, the computing system assigns the nodes in the Boolean network criticality values. The computing system determines a likelihood of a vulnerability in the netlist based upon the criticality values. The computing can output an indication as to whether the netlist is trusted based upon the determined likelihood of a vulnerability in the netlist.

Abstract: Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

Abstract: Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

Abstract: Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

Abstract: A method is disclosed for partitioning an input polytope into a conformal set of polytopes according to a subdivision pattern specified on lower-dimensional boundaries of the input polytope. A feature of this method is that it is applicable to any dimension. For input polytopes that are hexahedra isomorphic to a 3-dimensional cube, all members of the conforming partition will be hexahedra isomorphic to a 3-dimensional cube. A further feature of the invention is that it preserves convexity; a convex input polytope will result in a conformal partition comprising convex polytopes. Finally, the method may be used to process large conformal meshes of input polytopes in parallel and produce a globally conformal partition without the requirement of communication between processes.

Abstract: A method is disclosed for partitioning an input polytope into a conformal set of polytopes according to a subdivision pattern specified on lower-dimensional boundaries of the input polytope. A feature of this method is that it is applicable to any dimension. For input polytopes that are hexahedra isomorphic to a 3-dimensional cube, all members of the conforming partition will be hexahedra isomorphic to a 3-dimensional cube. A further feature of the invention is that it preserves convexity; a convex input polytope will result in a conformal partition comprising convex polytopes. Finally, the method may be used to process large conformal meshes of input polytopes in parallel and produce a globally conformal partition without the requirement of communication between processes.