Patents by Inventor Jacky Hung

Jacky Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100283622
    Abstract: A keyboard module adapted for connecting with a security unit is provided. The keyboard module includes a bottom plate, a plurality of buttons and a flexible circuit board. The buttons are disposed on the bottom plate, and the flexible circuit board is disposed between the bottom plate and the buttons. The flexible circuit board has a wire mesh circuit. The wire mesh circuit is adapted for electrically connecting with the security unit, so that the security unit generates a trigger signal while the wire mesh circuit is broken.
    Type: Application
    Filed: May 5, 2010
    Publication date: November 11, 2010
    Applicant: INVENTEC APPLIANCES CORP.
    Inventors: Yong-Feng Gu, Jacky Hung
  • Publication number: 20090064340
    Abstract: An apparatus to prevent smart cards from being read illegally is provided, wherein the apparatus is installed in a smart card reader comprises a CPU and a socket with a plurality of fingers, and the apparatus comprises: an electric circuits board (ECB), an inner circuit and a supplementary circuit. The ECB is disposed to cover the fingers and wired with an inner circuit electrically connected to a power supply. The supplementary circuit has an input terminal and an output terminal, wherein the input terminal is electrically connected to the power supply through the inner circuit of the ECB, and the output terminal is electrically connected to the CPU of the smart card reader; when the inner circuit is interrupted, an alarm signal is outputted by the supplementary circuit to the CPU to terminate the reading of the smart card by the smart card reader.
    Type: Application
    Filed: September 2, 2008
    Publication date: March 5, 2009
    Applicant: INVENTEC APPLIANCES CORP.
    Inventors: Tai-Shui Ho, Jacky Hung, Yong-Feng Gu
  • Patent number: 6552578
    Abstract: When the clock is stopped during a power-down mode, a clock duty-cycle detector asserts a power-down signal. The clock input is filtered to produce an average clock voltage over several clock periods. The average clock voltage is compared to an upper reference voltage to determine when the clock's duty cycle (high pulse-width percent) is above an upper limit. The average clock voltage is also compared to a lower reference voltage to determine when the clock's duty cycle is below a lower limit. When the clock's duty cycle is above the upper limit or below the lower limit the power-down signal is activated by logic. The logic disables the power-down signal when the clock's duty cycle is between the upper and lower limits. High-frequency clock glitches do not falsely trigger a power-up, since glitches are usually narrow and not sufficiently wide to reach the lower limit.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: April 22, 2003
    Assignee: Pericom Semiconductor Corp.
    Inventors: Jacky Hung-Yan Cheung, Hide Hattori