Patents by Inventor Jacky Pardillos

Jacky Pardillos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5642482
    Abstract: A system for transmitting data (NCC) between a computer bus (PSB) and a network (RE), including (1) a general purpose unit (GPU) connected to the bus and to a network-connected adapter, and including a first microprocessor and a unit for transferring frames between the bus and the adapter, and vice versa, comprising a dual port memory connected therebetween; and (2) a communication coprocessor (PPA) connected to the general purpose unit (GPU). Said coprocessor (PPA) includes a second microprocessor (CPU.sub.3) implementing, for each communication layer (C.sub.2 -C.sub.4), the corresponding protocol by providing each frame with control data adapted to said protocol, said second microprocessor being connected to the first microprocessor and the memory; and a third microprocessor (CPU.sub.4) providing direct memory access management of data transfer between the second microprocessor (CPU.sub.3) and the memory (VRAM).
    Type: Grant
    Filed: August 22, 1994
    Date of Patent: June 24, 1997
    Assignee: Bull, S.A.
    Inventor: Jacky Pardillos
  • Patent number: 5367646
    Abstract: An universal device (GPUI) for coupling a computer bus (PSB) to a controller (DEA) of a group of peripherals connected to one another by a specific link (FDDI) to which the controller is physically connected, includes a microprocessor (CPU) associated with a set of memories and an interface (IHAC, IHAD) for linkage with the controller (DEA) assuring the transfer of the data of the frames and of control blocks. The universal coupling device comprises a double-port random-access buffer memory (VRAM) connected by way of a first bus (B.sub.1) to the interface (IHAD) and by way of a second bus (B.sub.2) to the computer bus via a specific interface of the computer (MPC). Transfer of the data between the linking interface (IHAC, IHAD) and the double-port memory, on the one hand, and between the latter (VRAM) and the computer bus (PSB) on the other, is organized by a microprocessor (CPU), as is the conversion of control blocks used on the computer bus into those used in the link.
    Type: Grant
    Filed: July 15, 1992
    Date of Patent: November 22, 1994
    Assignee: Bull S.A.
    Inventors: Jacky Pardillos, Paul Ravaux