Patents by Inventor Jacob Anthony HERNANDEZ

Jacob Anthony HERNANDEZ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12069957
    Abstract: A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: August 20, 2024
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Jorge Vasquez, Bartlomiej Adam Kardasz, Jacob Anthony Hernandez, Thomas D. Boone, Georg Wolf, Mustafa Pinarbasi
  • Patent number: 11723217
    Abstract: A magnetic memory element has a Ru hard mask layer. The use of Ru advantageously allows for closer spacing of adjacent magnetic memory elements leading to increased data density. In addition, the use of Ru as a hard mask reduces parasitic electrical resistance by virtue of the fact that Ru does not oxidize in ordinary manufacturing environments. The magnetic memory element can be formed by depositing a plurality of memory element layers, depositing a Ru hard mask layer, depositing a RIEable layer over the Ru hard mask layer, and forming a photoresist mask over the hard mask layer. A reactive ion etching can be performed to transfer the image of the photoresist mask onto the RIEable layer to form a RIEable mask. An ion etching can then be performed to transfer the image of the RIAable mask onto the underlying Ru hard mask and underlying memory element layers.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: August 8, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Mustafa Pinarbasi, Jacob Anthony Hernandez, Cheng Wei Chiu
  • Publication number: 20220246842
    Abstract: A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.
    Type: Application
    Filed: April 15, 2022
    Publication date: August 4, 2022
    Inventors: Jorge Vasquez, Bartlomiej Adam Kardasz, Jacob Anthony Hernandez, Thomas D. Boone, Georg Wolf, Mustafa Pinarbasi
  • Publication number: 20220238601
    Abstract: A magnetic memory element has a Ru hard mask layer. The use of Ru advantageously allows for closer spacing of adjacent magnetic memory elements leading to increased data density. In addition, the use of Ru as a hard mask reduces parasitic electrical resistance by virtue of the fact that Ru does not oxidize in ordinary manufacturing environments. The magnetic memory element can be formed by depositing a plurality of memory element layers, depositing a Ru hard mask layer, depositing a RIEable layer over the Ru hard mask layer, and forming a photoresist mask over the hard mask layer. A reactive ion etching can be performed to transfer the image of the photoresist mask onto the RIEable layer to form a RIEable mask. An ion etching can then be performed to transfer the image of the RIAable mask onto the underlying Ru hard mask and underlying memory element layers.
    Type: Application
    Filed: April 15, 2022
    Publication date: July 28, 2022
    Inventors: Mustafa Pinarbasi, Jacob Anthony Hernandez, Cheng Wei Chiu
  • Patent number: 11329100
    Abstract: A magnetic memory element having a Ru hard mask layer. The use of Ru advantageously allows for closer spacing of adjacent magnetic memory elements leading to increased data density. In addition, the use of Ru as a hard mask reduces parasitic electrical resistance by virtue of the fact that Ru does not oxidize in ordinary manufacturing environments. The magnetic memory element can be formed by depositing a plurality of memory element layers, depositing a Ru hard mask layer, depositing a RIEable layer over the Ru hard mask layer, and forming a photoresist mask over the hard mask layer. A reactive ion etching can be performed to transfer the image of the photoresist mask onto the RIEable layer to form a RIEable mask. An ion etching can then be performed to transfer the image of the RIAable mask onto the underlying Ru hard mask and underlying memory element layers.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: May 10, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Mustafa Pinarbasi, Jacob Anthony Hernandez, Cheng Wei Chiu
  • Patent number: 11329217
    Abstract: A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: May 10, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Jorge Vasquez, Bartlomiej Adam Kardasz, Jacob Anthony Hernandez, Thomas D. Boone, Georg Wolf, Mustafa Pinarbasi
  • Patent number: 10903002
    Abstract: A method for manufacturing a magnetic memory element array that includes the use of a Ru hard mask layer and a diamond like carbon hard mask layer formed over the Ru hard mask layer. A plurality of magnetic memory element layers are deposited over a wafer and a Ru hard mask layer is deposited over the plurality of memory element layers. A layer of diamond like carbon is deposited over the Ru hard mask layer, and a photoresist mask is formed over the layer of diamond like carbon. A reactive ion etching is then performed to transfer the image of the photoresist mask onto the diamond like carbon mask, and an ion milling is performed to transfer the image of the patterned diamond like carbon mask onto the underlying Ru hard mask and memory element layers. The diamond like carbon mask can then be removed by reactive ion etching.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 26, 2021
    Assignee: SPIN MEMORY, INC.
    Inventors: Mustafa Pinarbasi, Jacob Anthony Hernandez, Elizabeth A. Dobisz, Thomas D. Boone
  • Publication number: 20200343298
    Abstract: A magnetic memory element having a Ru hard mask layer. The use of Ru advantageously allows for closer spacing of adjacent magnetic memory elements leading to increased data density. In addition, the use of Ru as a hard mask reduces parasitic electrical resistance by virtue of the fact that Ru does not oxidize in ordinary manufacturing environments. The magnetic memory element can be formed by depositing a plurality of memory element layers, depositing a Ru hard mask layer, depositing a RIEable layer over the Ru hard mask layer, and forming a photoresist mask over the hard mask layer. A reactive ion etching can be performed to transfer the image of the photoresist mask onto the RIEable layer to form a RIEable mask. An ion etching can then be performed to transfer the image of the RIAable mask onto the underlying Ru hard mask and underlying memory element layers.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 29, 2020
    Inventors: Mustafa Pinarbasi, Jacob Anthony Hernandez, Cheng Wei Chiu
  • Publication number: 20200343042
    Abstract: A method for manufacturing a magnetic memory element array that includes the use of a Ru hard mask layer and a diamond like carbon hard mask layer formed over the Ru hard mask layer. A plurality of magnetic memory element layers are deposited over a wafer and a Ru hard mask layer is deposited over the plurality of memory element layers. A layer of diamond like carbon is deposited over the Ru hard mask layer, and a photoresist mask is formed over the layer of diamond like carbon. A reactive ion etching is then performed to transfer the image of the photoresist mask onto the diamond like carbon mask, and an ion milling is performed to transfer the image of the patterned diamond like carbon mask onto the underlying Ru hard mask and memory element layers. The diamond like carbon mask can then be removed by reactive ion etching.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Inventors: Mustafa Pinarbasi, Jacob Anthony Hernandez, Elizabeth A. Dobisz, Thomas D. Boone
  • Patent number: 10777736
    Abstract: Described embodiments can be used in semiconductor manufacturing and employ materials with high and low polish rates to help determine a precise polish end point that is consistent throughout a wafer and that can cease polishing prior to damaging semiconductor elements. The height of the low polish rate material between the semiconductor elements is used as the polishing endpoint. Because the low polish rate material slows down the polishing process, it is easy to determine an end point and avoid damage to the semiconductor elements. An additional or alternative etch end point can be a thin layer of material that provides a very clear spectroscopy signal when it has been exposed, allowing the etch process to cease.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: September 15, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Mustafa Michael Pinarbasi, Jacob Anthony Hernandez, Arindom Datta, Marcin Jan Gajek, Parshuram Balkrishna Zantye
  • Patent number: 10734574
    Abstract: A perpendicular synthetic antiferromagnetic (pSAF) structure and method of making such a structure is disclosed. The pSAF structure comprises a first high perpendicular Magnetic Anisotropy (PMA) multilayer and a second high PMA layer separated by a thin Ruthenium layer. Each PMA layer is comprised of a first cobalt layer and a second cobalt layer separated by a nickel/cobalt multilayer. After each of the first and second PMA layers and the Ruthenium exchange coupling layer are deposited, the resulting structure goes through a high temperature annealing step, which results in each of the first and second PMA layers having a perpendicular magnetic anisotropy.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: August 4, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Bartlomiej Adam Kardasz, Mustafa Michael Pinarbasi, Jacob Anthony Hernandez
  • Publication number: 20200243757
    Abstract: A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 30, 2020
    Inventors: Jorge Vasquez, Bartlomiej Adam Kardasz, Jacob Anthony Hernandez, Thomas D. Boone, Georg Wolf, Mustafa Pinarbasi
  • Publication number: 20200035914
    Abstract: A perpendicular synthetic antiferromagnetic (pSAF) structure and method of making such a structure is disclosed. The pSAF structure comprises a first high perpendicular Magnetic Anisotropy (PMA) multilayer and a second high PMA layer separated by a thin Ruthenium layer. Each PMA layer is comprised of a first cobalt layer and a second cobalt layer separated by a nickel/cobalt multilayer. After each of the first and second PMA layers and the Ruthenium exchange coupling layer are deposited, the resulting structure goes through a high temperature annealing step, which results in each of the first and second PMA layers having a perpendicular magnetic anisotropy.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Applicant: Spin Memory, Inc.
    Inventors: Bartlomiej Adam KARDASZ, Mustafa Michael PINARBASI, Jacob Anthony HERNANDEZ
  • Patent number: 10468590
    Abstract: A perpendicular synthetic antiferromagnetic (pSAF) structure and method of making such a structure is disclosed. The pSAF structure can be a first high perpendicular Magnetic Anisotropy (PMA) multilayer and a second high PMA layer separated by a thin Ruthenium layer. Each PMA layer can be a first cobalt layer and a second cobalt layer separated by a nickel/cobalt multilayer. After each of the first and second PMA layers and the Ruthenium exchange coupling layer are deposited, the resulting structure goes through a high temperature annealing step, which results in each of the first and second PMA layers having a perpendicular magnetic anisotropy.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: November 5, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Bartlomiej Adam Kardasz, Mustafa Michael Pinarbasi, Jacob Anthony Hernandez
  • Publication number: 20170346002
    Abstract: Described embodiments can be used in semiconductor manufacturing and employ materials with high and low polish rates to help determine a precise polish end point that is consistent throughout a wafer and that can cease polishing prior to damaging semiconductor elements. The height of the low polish rate material between the semiconductor elements is used as the polishing endpoint. Because the low polish rate material slows down the polishing process, it is easy to determine an end point and avoid damage to the semiconductor elements. An additional or alternative etch end point can be a thin layer of material that provides a very clear spectroscopy signal when it has been exposed, allowing the etch process to cease.
    Type: Application
    Filed: August 11, 2017
    Publication date: November 30, 2017
    Inventors: Mustafa Michael Pinarbasi, Jacob Anthony Hernandez, Arindom Datta, Marcin Jan Gajek, Parshuram Balkrishna Zantye
  • Patent number: 9773974
    Abstract: Described embodiments can be used in semiconductor manufacturing and employ materials with high and low polish rates to help determine a precise polish end point that is consistent throughout a wafer and that can cease polishing prior to damaging semiconductor elements. The height of the low polish rate material between the semiconductor elements is used as the polishing endpoint. Because the low polish rate material slows down the polishing process, it is easy to determine an end point and avoid damage to the semiconductor elements. An additional or alternative etch end point can be a thin layer of material that provides a very clear spectroscopy signal when it has been exposed, allowing the etch process to cease.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: September 26, 2017
    Assignee: SPIN TRANSFER TECHNOLOGIES, INC.
    Inventors: Mustafa Michael Pinarbasi, Jacob Anthony Hernandez, Arindom Datta, Marcin Jan Gajek, Parshuram Balkrishna Zantye
  • Publication number: 20170033283
    Abstract: Described embodiments can be used in semiconductor manufacturing and employ materials with high and low polish rates to help determine a precise polish end point that is consistent throughout a wafer and that can cease polishing prior to damaging semiconductor elements. The height of the low polish rate material between the semiconductor elements is used as the polishing endpoint. Because the low polish rate material slows down the polishing process, it is easy to determine an end point and avoid damage to the semiconductor elements. An additional or alternative etch end point can be a thin layer of material that provides a very clear spectroscopy signal when it has been exposed, allowing the etch process to cease.
    Type: Application
    Filed: April 13, 2016
    Publication date: February 2, 2017
    Inventors: Mustafa Michael PINARBASI, Jacob Anthony HERNANDEZ, Arindom DATTA, Marcin Jan GAJEK, Parshuram Balkrishna ZANTYE
  • Publication number: 20160315118
    Abstract: A perpendicular synthetic antiferromagnetic (pSAF) structure and method of making such a structure is disclosed. The pSAF structure comprises a first high perpendicular Magnetic Anisotropy (PMA) multilayer and a second high PMA layer separated by a thin Ruthenium layer. Each PMA layer is comprised of a first cobalt layer and a second cobalt layer separated by a nickel/cobalt multilayer. After each of the first and second PMA layers and the Ruthenium exchange coupling layer are deposited, the resulting structure goes through a high temperature annealing step, which results in each of the first and second PMA layers having a perpendicular magnetic anisotropy.
    Type: Application
    Filed: April 6, 2016
    Publication date: October 27, 2016
    Inventors: Bartlomiej Adam KARDASZ, Mustafa Michael PINARBASI, Jacob Anthony HERNANDEZ