Patents by Inventor Jacob B. Leverich

Jacob B. Leverich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170031981
    Abstract: The disclosed embodiments relate to a system, a method and instructions embodied on a non-transitory computer-readable storage medium that facilitate executing an external command during query processing. While commencing execution of a query that streams data through a pipeline comprising consecutive commands that are chained together (including the external command), the system launches an external process that executes the external command. Next, as chunks of data are subsequently streamed through the pipeline during query processing, the system uses a transport protocol to communicate the chunks of data to and from the external process to facilitate executing the external command on the chunks of data, without terminating and re-launching the external process between chunks of data.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Applicant: SPLUNK INC.
    Inventors: Jacob B. Leverich, Itay A. Neeman, David R. Marquardt
  • Patent number: 8907462
    Abstract: An integrated circuit package includes a digital logic die disposed on a substrate; and an interposer die stacked vertically with the digital logic die on the substrate. The interposer die includes at least one vertical transistor configured to selectively provide electrical power to a portion of the digital logic die.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: December 9, 2014
    Assignee: Hewlett-Packard Development Company, L. P.
    Inventors: Matteo Monchiero, Jacob B. Leverich, Parthasarathy Ranganathan, Norman Paul Jouppi, Vanish Talwar
  • Patent number: 8812886
    Abstract: Various embodiments of the present invention are directed to methods that enable a memory controller to choose a particular operation mode for virtual memory devices of a memory module based on dynamic program behavior. In one embodiment, a method for determining an operation mode for each virtual memory device of a memory module includes selecting a metric (1001) that provides a standard by which performance and/or energy efficiency of the memory module is optimized during execution of one or more applications on a multicore processor. For each virtual memory device (1005), the method also includes collecting usage information (1006) associated with the virtual memory device over a period of time, determining an operation mode (1007) for the virtual memory device based on the metric and usage information, and entering the virtual memory device into the operation mode (1103, 1105, 1107, 1108).
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: August 19, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jung Ho Ahn, Norman P. Jouppi, Jacob B. Leverich, Robert S. Schreiber
  • Patent number: 8788747
    Abstract: Various embodiments of the present invention are directed a multi-core memory modules. In one embodiment, a memory module (500) includes at least one virtual memory device and a demultiplexer register (502) disposed between the at least one virtual memory device and a memory controller. The demultiplexer register receives a command identifying one of the at least one virtual memory devices from the memory controller and sends the command to the identified virtual memory device. In addition, the at least one virtual memory devices include at least one memory chip.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: July 22, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jung Ho Ahn, Norman P. Jouppi, Jacob B. Leverich
  • Publication number: 20110138387
    Abstract: Various embodiments of the present invention are directed to methods that enable a memory controller to choose a particular operation mode for virtual memory devices of a memory module based on dynamic program behavior. In one embodiment, a method for determining an operation mode for each virtual memory device of a memory module includes selecting a metric (1001) that provides a standard by which performance and/or energy efficiency of the memory module is optimized during execution of one or more applications on a multicore processor. For each virtual memory device (1005), the method also includes collecting usage information (1006) associated with the virtual memory device over a period of time, determining an operation mode (1007) for the virtual memory device based on the metric and usage information, and entering the virtual memory device into the operation mode (1103, 1105, 1107, 1108).
    Type: Application
    Filed: August 13, 2008
    Publication date: June 9, 2011
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Jung Ho Ahn, Norman P. Jouppi, Jacob B. Leverich, Robert S. Schreiber
  • Publication number: 20100194470
    Abstract: An integrated circuit package includes a digital logic die disposed on a substrate; and an interposer die stacked vertically with the digital logic die on the substrate. The interposer die includes at least one vertical transistor configured to selectively provide electrical power to a portion of the digital logic die.
    Type: Application
    Filed: February 5, 2009
    Publication date: August 5, 2010
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Matteo Monchiero, Jacob B. Leverich, Parthasarathy Ranganathan, Norman Paul Jouppi, Vanish Talwar