Abstract: A computing device comprising a controller is disclosed herein. The controller is to access print data of a virtual build volume including a 3D object to be generated by a 3D printer; modify the print data to include a 3D structure at a location within the build volume to encapsulate an amount of build material; receive powder degradation data corresponding to the powder degradation of the encapsulated amount of build material; and calibrate an additive manufacturing parameter based on the powder degradation data.

Abstract: An example system includes a simulation engine to determine a plurality of thermal states that will be experienced by powder at a voxel of a three-dimensional print volume as a result of printing a particular build. Each thermal state corresponds to a time during the printing or cooling from the printing. The system includes a stress engine to calculate a stress to the powder at the voxel based on the plurality of thermal states. The system includes a degradation engine to determine an amount of degradation of the powder at the voxel based on the stress.

Abstract: Cable assemblies for providing electrical communication between hinged sections of an electronic device are described. The cable assemblies can include a cover that covers one or more cables that run through a hinge region of the electronic device. The cable and cover can be drawn over a mandrel of the hinge region. The cover and the portions of the mandrel can be visible to a user at the hinge region of the electronic device. The cover can be sufficiently rigid to guide a path of the cable and protect the cable from bending beyond a prescribed angle during rotation of the electronic device at the hinge region. The cover can also be sufficiently rigid to prevent ceasing or folding of the cover and the cable during rotation of the electronic device at the hinge region.

Abstract: A multi-fluid kit for three-dimensional printing can include a fusing agent with water and a radiation absorber, and a detailing agent. The radiation absorber can absorb radiation energy and converts the radiation energy to heat. The detailing agent can include water and from about 0.1 wt % to about 20 wt % organosilanes based on a total weight of the detailing agent, wherein the organosilanes include an organosilane compound with a central silicon having both a water-solubilizing group and multiple hydrolyzable groups attached thereto.

Abstract: A system for predicting and summarizing medical events from electronic health records includes a computer memory storing aggregated electronic health records from a multitude of patients of diverse age, health conditions, and demographics including medications, laboratory values, diagnoses, vital signs, and medical notes. The aggregated electronic health records are converted into a single standardized data structure format and ordered arrangement per patient, e.g., into a chronological order. A computer (or computer system) executes one or more deep learning models trained on the aggregated health records to predict one or more future clinical events and summarize pertinent past medical events related to the predicted events on an input electronic health record of a patient having the standardized data structure format and ordered into a chronological order.

Abstract: Systems and methods are described for generating a dynamic label for a real-time communication session. An ongoing communication session is monitored to identify a content characteristic of the communication session. A size of a sliding window is determined based on the content characteristic, where the size of the sliding window defines a segment of the communication session to include in the most recent subset of communications. The most recent subset of communications is analyzed to identify relevant words based on one or more relevancy criteria. A dynamic label associated with the communication session is generated, where the dynamic label includes at least a selected one of the relevant words.

Abstract: A set of user interface tools is described facilitating asynchronous adjudication of one or more regions-of-interest in a medical image by a group of two or more graders, each of which has access to the set of tools in a workstation environment. The set of tools include (1) a feature for enabling the graders to assess the medical image and manually delineate one or more specific regions-of-interest (ROI) in the medical image, (2) a feature for assessing the ROI(s) delineated by other graders, including display of the ROI delineated by other graders; (3) dialog features for explaining and discussing the assessments, including a text feature for discussing the assessments. The dialog features and the ROIs delineated by all the graders are visible to all the graders on the workstation display as they collectively adjudicate the medical image in a round-robin manner. The set of tools further include (4) a feature for manually verifying grader agreement with the other graders' assessments.

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. Two wafers (and/or dies) are bonded together. A multi-via interconnect structure is formed extending from a backside of a first substrate to interconnect structures in the metallization layers on the first integrated circuit and the second integrated circuit. The multi-via interconnect structure may be formed by thinning a first substrate of a first wafer and forming a first opening through the first substrate. A second opening extends from the first opening to a first interconnect structure on the first wafer, and a third opening extends from the first interconnect structure on the first wafer to a second interconnect structure on the second wafer. The first, second, and third openings are filled with a conductive material, thereby forming a multi-via interconnect structure.

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. Two wafers (and/or dies) are bonded together. A multi-via interconnect structure is formed extending from a backside of a first substrate to interconnect structures in the metallization layers on the first integrated circuit and the second integrated circuit. The multi-via interconnect structure may be formed by thinning a first substrate of a first wafer and forming a first opening through the first substrate. A second opening extends from the first opening to a first interconnect structure on the first wafer, and a third opening extends from the first interconnect structure on the first wafer to a second interconnect structure on the second wafer. The first, second, and third openings are filled with a conductive material, thereby forming a multi-via interconnect structure.

Abstract: In an air nail gun, a stop ring is movably mounted around a movable seal member, which controls the supply of a compressed air into an air chamber to force a piston and a firing pin and to further drive a nail out of the air nail gun, having an upper inside wall disposed in contact with the movable seal member in an airtight status, a lower inside wall, and an inside annular flange disposed between the upper inside wall and the lower inside wall and protruding toward the movable seal member such that when the movable seal member is returned upon each nail firing action the stop ring is kept in position to prohibit the compressed air from moving through the movable seal member, and the movable seal member carries the stop ring toward a top block when an outside annular flange of the movable seal member touches the inside annular flange of the stop ring.

Abstract: A method of forming borderless contacts is provided. A substrate is provided. The substrate has at least a logic region and a memory region. A MOS transistor and a STI structure are formed on the logic region. The MOS transistor comprises a gate, a source/drain region and a cap insulating layer on the gate. An etching stop layer is formed on the substrate to cover the MSO transistor and the STI structure. A dielectric layer is formed in the etching stop layer. The dielectric layer, the etching stop layer and the cap insulating layer are partially removed to form a first opening according to the pattern of a first mask layer. The first opening exposes the gate. According to the pattern of a second mask layer, the dielectric layer and the etching stop layer are partially removed to form openings, which expose the source/drain region, in the dielectric layer.

Abstract: A method of manufacturing wells comprises the step of providing a p-type substrate and then sequentially forming a p-well and n-well with low dosage in the p-type substrate. Thereafter, energy is used to dope n-type ions into the p-well. The triple well formed in the present invention has low dosage ions, hence the DRAM formed on the triple well in subsequent process can have a faster refresh time.

Abstract: In a method of forming a salicide layer in an embedded dynamic random access memory, a thin oxide layer, a silicon nitride layer and a thick oxide layer are sequentially formed over a substrate after performing an annealing process to a source/drain region. The insulating layer on a gate and a source/drain region in a logic region and a gate in a memory region. Salicide layers are formed on the three regions mentioned above. Formation of the salicide layers can lower resistance of the three regions, increase speed and can avoid forming a salicide layer on the source/drain region in the memory region. Thus, current leakage can be avoided. In addition, the step of forming a salicide layer is conducted after the annealing process of the source/drain region, so problems of thermal stability and inter-diffusion of impurities in the polysilicon layer can also be solved.

Abstract: The invention provides a manufacturing method of forming a bottom plate for a capacitor on a substrate, wherein the substrate comprises a MOS transistor having a gate and a pair of source/drain regions. A crown-liked conductive plate is formed over an insulation oxide layer and a contact plug. The crown-liked conductive plate penetrates the insulation layer and the stop layer, wherein the bottom of the crown-like conductive plate is electrically connected to the contact plug. The crown-like conductive plate, served as the bottom plate for a DRAM capacitor, is composed of tungsten silicide or a combination of a tungsten nitride layer and a tungsten layer.

Abstract: A method of fabricating a self-aligned contact. A substrate is defined as a memory region and a logic region. Metal oxide semiconductors and source/drain regions are respectively formed in the memory region and in the logic region. A defined dielectric layer is formed over the substrate. Contact holes are respectively formed in the memory region and in the logic region until the source/drain regions are exposed. Silicide layers are formed over the contact holes. Portions of the silicide layer extend to surface of the dielectric layer neighboring the contact holes. A defined inter-layer dielectric layer is formed over the substrate. Vias are respectively formed in the memory region and in the logic region. The vias are filled with conductive layers. The self-aligned contact is formed.

Abstract: A method for forming a dual polycide gate. A substrate that has an isolation structure is provided, a polysilicon layer (or an &agr;-Si layer) is deposited over the substrate, N-type and P-type dopants are implanted into the polysilicon layer to form a dual gate having an N-type gate and a P-type gate. An annealing step is performed to restore the surface crystal structure of the polysilicon layer, an oxide layer is deposited on the doped polysilicon layer, and a silicide layer is formed over the oxide layer. The silicide layer, the oxide layer and the polysilicon layer are defined to form a polycide gate, a lightly doped source/drain region is formed beside the gate in the substrate. A spacer is formed on the sidewall of the gate, and a heavily doped source/drain region is formed beside the spacer in the substrate.

Abstract: A MOS gate manufacturing operation is capable of preventing acid corrosion and station contamination. The manufacturing method includes the steps of sequentially forming a polysilicon layer, a barrier layer, a silicide layer and a cap layer over a silicon substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the barrier layer. Finally, the substrate is cleaned following by the formation of a source/drain region having a lightly doped drain structure on each side of the gate. The thin oxide layer is capable of protecting the barrier layer against acid corrosion without causing any noticeable increase in gate conductivity.

Abstract: A manufacturing method is capable of preventing corrosion of a metal oxide semiconductor. The manufacturing method sequentially forms a polysilicon layer, a silicide layer and a top cap layer over a substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the silicide layer. Finally, the substrate is cleaned, and then of a source/drain region having a lightly doped drain structure is formed on each side of the gate.

Abstract: An improved formation method produces a metallic fuse capable of lowering the laser power needed for carrying out circuit repair. The method includes forming a metallic fuse when the penultimate metallic layer is formed. Since the metallic fuse is not too far away from the top surface, the power of the laser beam necessary for repairing the circuit can be moderate. Furthermore, the laser beam is more focused because it travels a shorter distance to reach the fuse, thereby avoiding unnecessary dispersion through intermediate material. Moreover, since the metallic fuse itself is not too thick, only a low-power laser beam is needed to melt the metallic fuse.

Abstract: A method includes a self-aligned silicide (Salicide) technology in fabrication of an embedded dynamic random access memory (DRAM). On a silicon wafer, a first MOS transistor is formed in a logic device region, and second MOS transistor is formed in a memory device region. The improved method includes forming an insulating layer over the substrate at least covering the first (second) MOS transistor. A top portion of the insulating layer is removed to expose only a top portion of the first (second) gate structure. A portion of the insulating layer covering the first MOS transistor is removed to expose the first MOS transistor. Using the remaining insulating layer on the second MOS transistor as a mask, the Salicide fabrication process is performed to form a self-aligned silicide layer on the first interchangeable source/drain region, and the exposed top surface of the first (second) polysilicon gate structure.