Abstract: A combination CMP-etch method for forming a thin planar layer over the surface of a device includes the steps of providing a substrate including a plurality of surface projections defining gaps therebetween, forming an etchable layer on the substrate, performing a CMP process on the etchable layer to form a planar layer having a first thickness in excess of 1,000 Angstroms, and etching the planar layer to a second thickness less than 1,000 Angstroms. In a particular method, the step of forming the etchable layer includes the steps of forming an etch resistant layer on the substrate, forming a fill layer on the etch-resistant layer, etching the fill layer to expose portions of the etch-resistant layer overlying the projections, and to leave a portion of the fill layer in the gaps, and forming the etchable layer on the exposed portions of the etch-resistant layer and the fill layer.

Abstract: A method for manufacturing a planar reflective light valve backplane includes the steps of providing a substrate (e.g., a reflective backplane) including a plurality of surface projections (e.g., pixel mirrors) defining gaps therebetween, forming an etch-resistant layer on the substrate, forming a fill layer on the etch resistant layer, and etching the fill layer to expose portions of the etch resistant layer overlying the projections, leaving a portion of the fill layer in the gaps. A particular method includes an optional step of forming a protective layer over the exposed portions of the etch-resistant layer and the fill layer. In another particular method, the etch resistant layer includes an optical thin film layer and an etch-resistant cap layer.

Abstract: A planar wafer based device (e.g., a reflective light valve backplane) includes a substrate having a plurality of surface projections (e.g., pixel mirrors) defining gaps therebetween, an etch-resistant layer formed on the substrate, and a fill layer formed on a portion of the etch-resistant layer in the gaps. In a particular embodiment, the fill layer is a spin-on coating. An optional protective layer formed on the exposed portions of the etch-resistant layer and the fill layer protects the underlying layers during subsequent processing steps.

Abstract: According to one aspect of the invention, a method of fabricating N+ and P+ silicided gates limits diffusion when using a Tungsten, Titanium or Cobalt silicide in the gate fabrication. An example method involves doping a polysilicon structure in first and second dual gate regions and on either side of an undoped polysilicon region, forming a silicide is over the polysilicon structure, and then stuffing the undoped polysilicon region with a species selected to inhibit lateral diffusion of dopant from the polysilicon in the silicide. Subsequently, each gate is completed so that is includes a dielectric layer arranged over the silicide and one of the doped gate poly regions. Applications include logic circuits having embedded-DRAM, and circuits directed to stand-alone logic or stand-alone DRAM.