Patents by Inventor Jacob Doweck

Jacob Doweck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200204356
    Abstract: A processor includes a processor core. A register of the core is to store: a bit range for a number of address bits of physical memory addresses used for key identifiers (IDs), and a first key ID to identify a boundary between non-restricted key IDs and restricted key IDs of the key identifiers. A memory controller is to: determine, via access to bit range and the first key ID in the register, a key ID range of the restricted key IDs within the physical memory addresses; access a processor state that a first logical processor of the processor core executes in an untrusted domain mode; receive a memory transaction, from the first logical processor, including an address associated with a second key ID; and generate a fault in response to a determination that the second key ID is within a key ID range of the restricted key IDs.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Inventors: Ido OUZIEL, Arie AHARON, Dror CASPI, Baruch CHAIKIN, Jacob DOWECK, Gideon GERZON, Barry E. HUNTLEY, Francis X. MCKEEN, Gilbert NEIGER, Carlos V. ROZAS, Ravi L. SAHITA, Vedvyas SHANBHOGUE, Assaf ZALTSMAN
  • Publication number: 20200201786
    Abstract: Implementations described provide hardware support for the co-existence of restricted and non-restricted encryption keys on a computing system. Such hardware support may comprise a processor having a core, a hardware register to store a bit range to identify a number of bits, of physical memory addresses, that define key identifiers (IDs) and a partition key ID identifying a boundary between non-restricted and restricted key IDs. The core may allocate at least one of the non-restricted key IDs to a software program, such as a hypervisor. The core may further allocate a restricted key ID to a trust domain whose trust computing base does not comprise the software program. A memory controller coupled to the core may allocate a physical page of a memory to the trust domain, wherein data of the physical page of the memory is to be encrypted with an encryption key associated with the restricted key ID.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Inventors: Ido OUZIEL, Arie AHARON, Dror CASPI, Baruch CHAIKIN, Jacob DOWECK, Gideon GERZON, Barry E. HUNTLEY, Francis X. MCKEEN, Gilbert NEIGER, Carlos V. ROZAS, Ravi L. SAHITA, Vedvyas SHANBHOGUE, Assaf ZALTSMAN, Hormuzd M. KHOSRAVI
  • Patent number: 10223121
    Abstract: A processor includes a decoder, a data return buffer, and an execution unit. The decoder is to decode an instruction for a non-posted load into a decoded instruction for loading data from memory mapped input/output. The execution unit is for executing the decoded instruction. The execution is to start a timer, determine whether the timer exceeds a timeout threshold, allocate an entry in the data return buffer for the load, and determine whether an event arrived. The timer is to measure an amount of time taken to return the non-posted load instruction. The determination whether an event arrived is made in response to at least one of the allocation of the entry for the load, or a determination that the timer exceeds the timeout threshold.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Ido Ouziel, Raanan Sade, Jacob Doweck
  • Publication number: 20180181393
    Abstract: A processor includes a decoder, a data return buffer, and an execution unit. The decoder is to decode an instruction for a non-posted load into a decoded instruction for loading data from memory mapped input/output. The execution unit is for executing the decoded instruction. The execution is to start a timer, determine whether the timer exceeds a timeout threshold, allocate an entry in the data return buffer for the load, and determine whether an event arrived. The timer is to measure an amount of time taken to return the non-posted load instruction. The determination whether an event arrived is made in response to at least one of the allocation of the entry for the load, or a determination that the timer exceeds the timeout threshold.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Ido Ouziel, Raanan Sade, Jacob Doweck
  • Publication number: 20180060246
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
    Type: Application
    Filed: November 3, 2017
    Publication date: March 1, 2018
    Applicant: Intel Corporation
    Inventors: Ben-Zion Friedman, Jacob Doweck, Eliezer Weissmann, James B. Crossland, Ohad Falik
  • Publication number: 20160041921
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
    Type: Application
    Filed: October 19, 2015
    Publication date: February 11, 2016
    Applicant: INTEL CORPORATION
    Inventors: Ben-Zion Friedman, Jacob Doweck, Eliezer Weissmann, James B Crossland, Ohad Falik
  • Publication number: 20160011874
    Abstract: A processing device implementing silent memory instructions and miss-rate tracking to optimize switching policy on threads is disclosed. A processing device of the disclosure includes a branch prediction unit (BPU) to predict that an instruction of a first thread in a current execution context of the processing device is a delinquent instruction, indicate that the first thread including the delinquent instruction is in a silent execution mode, indicate that the delinquent instruction is to be executed as a silent instruction, switch an execution context of the processing device to a second thread, and when the execution context returns to the first thread, cause the delinquent instruction to be re-executed as a regular instruction.
    Type: Application
    Filed: July 9, 2014
    Publication date: January 14, 2016
    Inventors: DORON ORENSTEIN, TOMER STARK, CHEN DAN, JACOB DOWECK, ENRIC G. CODINA, JOSEP M. CODINA, REKAI GONZALEZ-ALBERQUILLA, TANAUSU RAMIREZ
  • Patent number: 9164917
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: October 20, 2015
    Assignee: Intel Corporation
    Inventors: Ohad Falik, Ben-Zion Friedman, Jacob Doweck, Eliezer Weissmann, James B Crossland
  • Patent number: 9164916
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: October 20, 2015
    Assignee: Intel Corporation
    Inventors: Ohad Falik, Ben-Zion Friedman, Jacob Doweck, Eliezer Weissmann, James B Crossland
  • Patent number: 9076019
    Abstract: A method and apparatus to provide cryptographic integrity checks and replay protection to protect against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a “time stamp” indicator. A tree-based replay protection scheme uses standard XTS-AES to encrypt contents of a cache line in the system memory. A Message-Authentication Code (MAC) for the cache line is encrypted using enhanced XTS-AES and a “time stamp” indicator associated with the cache line. The “time stamp indicator” is stored in a processor.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Uday Savagaonkar, Francis X. McKeen, Carlos V. Rozas, David M. Durham, Jacob Doweck, Ofir Mulla, Ittai Anati, Zvika Greenfield, Moshe Maor
  • Publication number: 20140351554
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 27, 2014
    Applicant: Intel Corporation
    Inventors: Ohad Falik, Ben-Zion Friedman, Jacob Doweck, Eliezer Weissmann, James B Crossland
  • Publication number: 20140351553
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 27, 2014
    Applicant: Intel Corporation
    Inventors: Ohad Falik, Ben-Zion Friedman, Jacob Doweck, Eliezer Weissmann, James B Crossland
  • Patent number: 8812823
    Abstract: A memory access management technique is disclosed, one embodiment of which relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. A processor may include load buffer entries having predictor table entries associated therewith, including saturation counters to record history of previous conflicts between loads and stores corresponding to the same target address. A watchdog unit may disable memory disambiguation (MD) if the MD causes too high a misprediction rate for load operation and store operation conflicts. In one embodiment, the MD is disabled if a flush counter value reaches a threshold.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: August 19, 2014
    Assignee: Intel Corporation
    Inventors: Evgeni Krimer, Guillermo Savransky, Idan Mondjak, Jacob Doweck
  • Publication number: 20140223197
    Abstract: A method and apparatus to provide cryptographic integrity checks and replay protection to protect against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a “time stamp” indicator. A tree-based replay protection scheme uses standard XTS-AES to encrypt contents of a cache line in the system memory. A Message-Authentication Code (MAC) for the cache line is encrypted using enhanced XTS-AES and a “time stamp” indicator associated with the cache line. The “time stamp indicator” is stored in a processor.
    Type: Application
    Filed: June 29, 2011
    Publication date: August 7, 2014
    Inventors: Shay Gueron, Uday Savagaonkar, Francis X. McKeen, Carlos V. Rozas, David M. Durham, Jacob Doweck, Ofir Mulla, Ittai Anati, Zvika Greenfield, Moshe Maor
  • Patent number: 8549263
    Abstract: A memory access management technique is disclosed, one embodiment of which relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. A processor may include load buffer entries having predictor table entries associated therewith, including saturation counters to record history of previous conflicts between loads and stores corresponding to the same target address. A watchdog unit may disable memory disambiguation (MD) if the MD causes too high a misprediction rate for load operation and store operation conflicts. In one embodiment, the MD is disabled if a flush counter value reaches a threshold.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: October 1, 2013
    Assignee: Intel Corporation
    Inventors: Evgeni Krimer, Guillermo Savransky, Idan Mondjak, Jacob Doweck
  • Patent number: 8468365
    Abstract: A method and apparatus for protecting against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a “time stamp” indicator. An incrementing mechanism using the “time stamp” indicator generates a tweak which separates different contexts over different times such that the effect of “Type 2 replay attacks” is mitigated.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: June 18, 2013
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Gideon Gerzon, Ittai Anati, Jacob Doweck, Moshe Maor
  • Publication number: 20120079285
    Abstract: A method and apparatus for protecting against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a “time stamp” indicator. An incrementing mechanism using the “time stamp” indicator generates a tweak which separates different contexts over different times such that the effect of “Type 2 replay attacks” is mitigated.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: SHAY GUERON, GIDEON GERZON, ITTAI ANATI, JACOB DOWECK, MOSHE MAOR
  • Publication number: 20110035564
    Abstract: A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address.
    Type: Application
    Filed: October 19, 2010
    Publication date: February 10, 2011
    Inventors: Evgeni Krimer, Guillermo Savransky, Idan Mondjak, Jacob Doweck
  • Publication number: 20090282202
    Abstract: A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address.
    Type: Application
    Filed: July 14, 2009
    Publication date: November 12, 2009
    Inventors: Evgeni Krimer, Guillermo Savransky, Idan Mondjak, Jacob Doweck
  • Patent number: 7590825
    Abstract: Memory access management techniques are described. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. In an embodiment, a load operation may be predicted to not conflict with older pending store operations if a saturation counter corresponding to the load operation is below a threshold value and a maximum rate of mispredictions has not occurred. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: September 15, 2009
    Assignee: Intel Corporation
    Inventors: Evgeni Krimer, Guillermo Savransky, Idan Mondjak, Jacob Doweck