Abstract: A method for fetching information in response to hazard indication information, the method includes: (i) associating hazard indication information to at least one information unit that is being fetched to the cache module; (ii) receiving a request to perform a fetch operation; and (iii) determining whether to fetch at least one information unit to the cache module in response to the hazard indication information and in response to dirty information associated with the at least one information unit.

Abstract: Apparatus and method for bus matching. The method includes: receiving data transfer characteristics at a first endian mode and at a second endian mode; determining a connectivity of multiple devices to an interfacing bus in response to the data transfer characteristics and in response to a relationship between a width of the interfacing bus and a width of each device interface; wherein at least one device interface is connected in parallel to multiple interfacing bus portions; and configuring a control logic such as to provide control signals representative of a transfer of data over the interfacing bus; whereas the control logic is configured in response to the connectivity.

Abstract: A virtual address cache and a method for sharing data. The virtual address cache includes: a memory, adapted to store virtual addresses, task identifiers and data associated with the virtual addresses and the task identifiers; and a comparator, connected to the memory, adapted to determine that data associated with a received virtual address and a received task identifier is stored in the memory if at least a portion of the received virtual address equals at least a corresponding portion of a certain stored virtual address and a stored task identifier associated with the certain stored virtual address indicates that the data is shared between multiple tasks.

Abstract: A memory management unit that includes: (i) multiple data segment descriptors, each data segment descriptor associated with a data memory segment; (ii) multiple program segment descriptors, each program segment descriptor associated with a program memory segment; and (iii) a controller, adapted to replace the content of the multiple data segment descriptors and the multiple program segment descriptors in response to a task switch.

Abstract: A memory management unit that includes: (i) multiple data segment descriptors, each data segment descriptor associated with a data memory segment; (ii) multiple program segment descriptors, each program segment descriptor associated with a program memory segment; and (iii) a controller, adapted to replace the content of the multiple data segment descriptors and the multiple program segment descriptors in response to a task switch.

Abstract: A virtual address cache comprising a comparator arranged to receive a virtual address for addressing data associated with a task and a memory, wherein the comparator is arranged to make a determination as to whether data associated with the received virtual address is stored in the memory based upon an indication that the virtual address is associated with data shared between a first task and a second task and a comparison of the received virtual address with an address associated with data stored in memory.

Abstract: A method and apparatus non-intrusive tracing. The method includes: counting selected events by multiple counters; sampling the multiple counters to retrieve multiple counter values in response to predefined triggering events; receiving additional trace information that comprises at least one program counter value, and outputting, as a trace information, at least one of the multiple counters values and the additional trace information.

Abstract: A method and apparatus non-intrusive tracing. The method includes: counting selected events by multiple counters; sampling the multiple counters to retrieve multiple counter values in response to predefined triggering events; receiving additional trace information that comprises at least one program counter value, and outputting, as a trace information, at least one of the multiple counters values and the additional trace information.

Abstract: A method for fetching information in response to hazard indication information, the method includes: (i) associating hazard indication information to at least one information unit that is being fetched to the cache module; (ii) receiving a request to perform a fetch operation; and (iii) determining whether to fetch at least one information unit to the cache module in response to the hazard indication information and in response to dirty information associated with the at least one information unit.

Abstract: Read/write conflicts in an instruction cache memory (11) are reduced by configuring the memory as two even and odd array sub-blocks (12,13) and adding an input buffer (10) between the memory (11) and an update (16). Contentions between a memory read and a memory write are minimised by the buffer (10) shifting the update sequence with respect to the read sequence. The invention can adapt itself for use in digital signal processing systems with different external memory behaviour as far as latency and burst capability is concerned.

Abstract: A processing system has a processor, a cache, and a fetch unit. If there is a miss in the cache, the fetch unit generates a fetch address for the miss in the cache for the purpose of retrieving the requested data from external memory and providing the data to the processor and loading the data in a location in a line in the cache. The fetch unit also generates additional prefetch addresses for addresses consecutive with the fetch address. The prefetch addresses continue to be generated for all of the locations in the line in the cache that are consecutive with the fetch address. The generation of prefetch addresses will be stopped if another requests arrives that is not part of the already generated prefetched addresses. Further, the outstanding prefetches will be terminated if the external memory can handle such termination.

Abstract: A processing system has a processor, a cache, and a fetch unit. If there is a miss in the cache, the fetch unit generates a fetch address for the miss in the cache for the purpose of retrieving the requested data from external memory and providing the data to the processor and loading the data in a location in a line in the cache. The fetch unit also generates additional prefetch addresses for addresses consecutive with the fetch address. The prefetch addresses continue to be generated for all of the locations in the line in the cache that are consecutive with the fetch address. The generation of prefetch addresses will be stopped if another requests arrives that is not part of the already generated prefetched addresses. Further, the outstanding prefetches will be terminated if the external memory can handle such termination.