Abstract: An electronic computer aided design system provides for automated operation of a plurality of design tools to produce multiply design solutions to an initial circuit layout. Through the user entry of relative weights for: power, timing and area, different solutions to an initial layout can be generated exhibiting the requested balance of improvements over the original layout. A novel parts placement process is disclosed which prioritizes the reconfiguration of the initial design in a manner which assures that the multiple solutions will be generated which exhibit improved performance over the original layout in accordance with the priorities established by the user.

Abstract: A system is disclosed for compacting an initial electronic layout of cells within an initial layout boundary. The system includes forming paths extending from a bottom edge of the layout to a top edge. The paths intersect cells of the initial layout. The system determines which of the paths are critical paths. Critical cuts are then determined. A critical cut is a cut that severs critical paths. A set of cells associated with a critical cut are removed from the layout and replaced in order to reduce the initial layout boundary.

Abstract: The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveability, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.

Abstract: An automated routing tool for routing interconnections between circuit elements, standard cells and/or cell blocks of cell-based designs which incorporates the best features of both currently known gate array routing techniques with currently known cell-based routing techniques. The invention eliminates the disadvantages of permitting the detailed router to adjust the relative positions of the circuit elements, standard cells and/or cell blocks during the detailed routing process. The method employs a topology manager which iteratively compacts the circuit topology while at the same time optimizing the routing of the interconnections among the circuit elements, standard cells and/or cell blocks of the circuit design. The method employs bin-based global routing, which identifies expandable boundaries and which provides input to a compaction routine which expands or contracts the expandable areas in accordance with the result of the global routing process.

Abstract: The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveabilility, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.