Abstract: A bit synchronizer for a BPSK input signal having a sinusoidal carrier frequency f that is much greater than the modulating signal bit rate. The synchronizer comprises means (29, 31) for repetitively sampling the amplitude of the input signal over a preselected sampling interval portion of each modulating signal bit period (T). For each sampling interval, three numbers are recorded: N1, the total number of samples; N2, the number of samples that do not change sign with respect to a reference sample; and N3, the number of samples that do change sign with respect to the reference sample. When the number of samples not changing sign exceeds a preselected threshold value, which takes into account noise corruption of the input signal, bit synchronization is declared, a synchronized output clock (39) is generated, and digital data having a 180.degree. ambiguity is sent to subsequent ambiguity resolution means.

Abstract: A soft digital limiter (2) for limiting an analog input signal (1) from a maximum expected range (61) to a useful range (60). The number (m) of desired levels of resolution in the limiter (2) is preselected to be any power of two. An analog-to-digital converter (9) converts the input analog signal (1) to a digital representation (20). The converter (9) has its input voltage rating matched to the maximum expected range (61) and its output resolution matched to the preselected degree (m) of resolution. In the preferred two's complement numbering system, the condition for the input signal (1) falling within the useful range (60) is that the most significant p+1 bits of the digital representation (20) are all identical, where p is the number of bits required by the converter (9) to delineate that portion of the maximum expected range (61) outside of the useful range (60). A network of comparators (e.g., 38, 39) implements this condition.