Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the columm direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the columm direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract: The present invention relates to semiconductor devices in general, and more particularly to semiconductor devices having anti-reflective coatings to aid in the patterning of a reflective layer thereon to form, for example, a gate electrode. The invention also relates to methods for making a semiconductor having a patterned reflective layer.

Abstract: Disclosed is a process for making a self-aligning conductive via structure in a semiconductor device. The process includes forming a first interconnect metallization layer over an oxide layer. Forming an etch stop layer over the first interconnect metallization layer. Forming a conductive via metallization layer over the etch stop layer. Forming a hard mask layer over the conductive via metallization layer. The process further includes producing a conductive via and an interconnect line, where the conductive via is formed from a portion of the conductive via metallization layer, and the interconnect line is formed from a portion of the first interconnect metallization layer. The conductive via is substantially aligned with the underlying interconnect line.

Abstract: A method for fabricating a semiconductor integrated circuit structure having a reduced width gate electrode. A pre-gate electrode having a width is first delineated by conventional lithography techniques. The conductive layer is partially etched to expose a first and second pre-gate side wall. With the pre-gate side walls exposed, the structure is oxidized to grow an oxide layer on the pre-gate side walls, thereby consuming a predetermined amount of the conductive material. The newly formed oxide layer is then removed to reduce the pre-gate width while retaining at least a portion of an oxide layer above the conductive layer as a mask. The reduced width gate electrode is completed by etching the remaining unmasked conductive layer.