Abstract: A network switching system includes transceiver devices respectively provided for a plurality of input line cards. The switching system also includes transceiver devices respective provided for a plurality of output line cards. The switching system further includes a switch device communicatively coupled to each of the plurality of input line cards and the plurality of output line cards. The switch device includes a crosspoint matrix for communicatively connecting one of the input line cards to one of the output line cards. The switch device is capable of operating in either a crosspoint mode for routing cells or packets from one of the input line cards to one of the output line cards, or a scheduler mode for controlling flow of cells and/or packets through at least one other switch device.

Abstract: Embodiments to perform improved error control using packet fragments are described. The apparatus may include a padding module to add a pad byte to uneven packet fragments of a packet, a partial checksum generator module to generate a partial error control value for each packet fragment, a pseudo-header generator module to generate a pseudo header for the packet, and a partial checksum combiner module to combine the partial error control values into an error control value. Other embodiments are described and claimed.

Abstract: Embodiments to perform improved error control using packet fragments are described. The apparatus may include a padding module to add a pad byte to uneven packet fragments of a packet, a partial checksum generator module to generate a partial error control value for each packet fragment, a pseudo-header generator module to generate a pseudo header for the packet, and a partial checksum combiner module to combine the partial error control values into an error control value. Other embodiments are described and claimed.

Abstract: A protocol processing system includes a frame buffer controller to store data. A protocol terminator system is coupled to the frame buffer controller to receive and transmit events. An event queue system is coupled to the protocol terminator system to store the events in an event queue. A protocol processing agent is provided to process a protocol. The protocol processing agent has a first connection with the frame buffer controller and a second connection with the protocol terminator system. The first connection transports the data between the protocol processing agent and the frame buffer controller, and the second connection transports the events between the protocol processing agent and the protocol terminator system.

Abstract: A network processor application-specific integrated circuit (ASIC) includes a plurality of processor devices each adapted to generate a semaphore operation request. A request arbiter, having connections to the plurality of processor devices, is provided to determine the semaphore operation request from one of the plurality of processor devices to be forwarded. A content addressable memory (CAM) is provided to store a data set. A CAM control state machine interconnects the request arbiter and the CAM, and implements a semaphore operation requested by one of the plurality of processor devices to the content addressable memory to access the data set.

Abstract: Embodiments to perform improved error control using packet fragments are described.

Abstract: A memory that supports non-aligned memory accesses includes a field address generator circuit, multiple field memories, and a data rotation circuit. The field address generator circuit generates multiple field addresses in response to an address associated with a memory access. Each field memory receives one of the field addresses from the field address generator circuit. The data rotation circuit rotates data associated with the memory access based upon the memory access address to support a non-aligned access. The memory can support either non-aligned read accesses or non-aligned write accesses. A method for performing non-aligned read or write memory accesses is also described.

Abstract: A key lookup system to look up keys associated with a plurality of frames of data includes a key source device that provides source keys to the system. A memory stores data keys and data associated therewith. A plurality of lookup engines searches for the data keys in the memory that are identical to the source keys. A Content Addressable Memory (CAM) stores a copy of a source key being searched for by one of the plurality of lookup engines. A CAM check device to determine whether a key identical to the source key is located in the CAM. A key insertion device copies the source key into the CAM and into one of the plurality of lookup engines if the key identical to the source key is not found in the CAM.

Abstract: A network processor application-specific integrated circuit (ASIC) includes a plurality of processor devices each adapted to generate a semaphore operation request. A request arbiter, having connections to the plurality of processor devices, is provided to determine the semaphore operation request from one of the plurality of processor devices to be forwarded. A content addressable memory (CAM) is provided to store a data set. A CAM control state machine interconnects the request arbiter and the CAM, and implements a semaphore operation requested by one of the plurality of processor devices to the content addressable memory to access the data set.

Abstract: A protocol processing system includes a frame buffer controller to store data. A protocol terminator system is coupled to the frame buffer controller to receive and transmit events. An event queue system is coupled to the protocol terminator system to store the events in an event queue. A protocol processing agent is provided to process a protocol. The protocol processing agent has a first connection with the frame buffer controller and a second connection with the protocol terminator system. The first connection transports the data between the protocol processing agent and the frame buffer controller, and the second connection transports the events between the protocol processing agent and the protocol terminator system.

Abstract: A memory that supports non-aligned memory accesses includes a field address generator circuit, multiple field memories, and a data rotation circuit. The field address generator circuit generates multiple field addresses in response to an address associated with a memory access. Each field memory receives one of the field addresses from the field address generator circuit. The data rotation circuit rotates data associated with the memory access based upon the memory access address to support a non-aligned access. The memory can support either non-aligned read accesses or non-aligned write accesses. A method for performing non-aligned read or write memory accesses is also described.