Abstract: A packet processor of a network device receives packets ingressing from a plurality of network links via a plurality of network ports of the network device. The packet processor buffers the packets in an internal packet memory in a plurality of queues, including a first queue. In response to the packet processor detecting congestion in the internal packet memory, the packet processor selectively forwards a group of multiple packets in the first queue from the internal packet memory to a first port, among one or more ports coupled to one or more external memories, to transfer the group of multiple packets to a first external memory that is coupled to the first port so that the first queue is stored across the internal packet memory and the first external packet memory.

Abstract: A network device transfers packets from a packet memory to one or more network interfaces for transmission by the one or more network interfaces. The transferring of packets includes transferring the packets via one or more respective transmit data paths that correspond to one or more respective network interfaces. The network device measures one or more respective amounts of time required to transmit respective packet data within the one or more respective transmit data paths. The network device uses the one or more respective measured amounts of time to determine when to start transfer of packets from the packet memory to the one or more network interfaces via the one or more respective transmit data paths.

Abstract: A packet processor of a network device receives packets ingressing from a plurality of network links via a plurality of network ports of the network device. The packet processor buffers the packets in an internal packet memory in a plurality of queues, including a first queue. In response to the packet processor detecting congestion in the internal packet memory, the packet processor selectively forwards a group of multiple packets in the first queue from the internal packet memory to a first port, among one or more ports coupled to one or more external memories, to transfer the group of multiple packets to a first external memory that is coupled to the first port so that the first queue is stored across the internal packet memory and the first external packet memory.

Abstract: A packet group processor of a network device defines groups of packets among packets that are being processed by the network device, each of at least some of the groups of packets defining a respective group of at least two different packets. Each group includes one or more packets to be transmitted via a respective same network interface. A transmit processor makes a single transmit decision that a particular group of at least two packets is to be transmitted via a corresponding network interface, and in response to the single transmit decision, transfers the particular group of at least two packets to the corresponding network interface for transmission.

Abstract: Packets to be transmitted from a network device are buffered in queues in a first packet memory. In response to detecting congestion in a queue in the first packet memory, groups of multiple packets are transferred from the first packet memory to a second packet memory, the second packet memory configured to buffer a portion of traffic bandwidth supported by the network device. Prior to transmission of the packets among the one or more groups of multiple packets from the network device, packets among the one or more groups of multiple packets are transferred from the second packet memory back to the first packet memory. The packets transferred from the second packet memory back to the first packet memory are retrieved from the first packet memory and are forwarded to one or more network ports for transmission of the packets from the network device.

Abstract: Packets to be transmitted from a network device are buffered in queues in a first packet memory. In response to detecting congestion in a queue in the first packet memory, groups of multiple packets are transferred from the first packet memory to a second packet memory, the second packet memory configured to buffer a portion of traffic bandwidth supported by the network device. Prior to transmission of the packets among the one or more groups of multiple packets from the network device, packets among the one or more groups of multiple packets are transferred from the second packet memory back to the first packet memory. The packets transferred from the second packet memory back to the first packet memory are retrieved from the first packet memory and are forwarded to one or more network ports for transmission of the packets from the network device.

Abstract: Packet data corresponding to a multicast (MC) packet received by a network device is stored in a packet memory. A header of the MC packet is analyzed to determine two or more ports via which the MC packet is to be transmitted. It is determined that two or more pending read requests are to read packet data from a particular memory location in the packet memory. In response to determining that the two or more pending read requests are to read packet data from the particular memory location, the packet data is read a single time from the particular memory location. Respective instances of the packet data read from the particular memory location are provided to respective two or more read client devices for subsequent transmission of the packet data via the two or more ports determined by the packet processor.

Abstract: A method for deallocating memory in a first network device is described. A multicast packet is received and stored in memory cells. Egress descriptors corresponding to the multicast packet are generated for transmission of the multicast packet. A final count of the egress descriptors is determined. The egress descriptors are processed for transmission of the multicast packet and a value of a signed reference counter corresponding to the multicast packet is updated in a first direction before the final count has been determined and after a copy of the multicast packet has been received by an egress port of the first network device. The value of the signed reference counter is updated in a second direction opposite the first direction by the final count after determination of the final count. The memory cells are deallocated when cumulative first direction updates are equal to the second direction update.

Abstract: An integrated circuit device includes dispatcher circuitry that receives signals from a first number of sources, multiplexes the signals into a single mixed signal in a predetermined order, and transmits the mixed signal to a destination via a mixed signal interface having an arbitrary length and operating at an interface clock frequency equal to a product of a device clock frequency and the first number. A second number of samplers is disposed in series along the mixed signal interface, outputting a sampled mixed signal synchronized to the interface clock. A chain of tracking elements in series, corresponding in number to the second number, outputs a tracking indication separate from the sampled mixed signal. Capture circuitry demultiplexes the sampled mixed signal into a plurality of demultiplexed signals, according to a starting point based on the tracking indication, onto a plurality of signal buses corresponding in number to the first number.

Abstract: Packet data corresponding to a multicast (MC) packet received by a network device is stored in a packet memory. A header of the MC packet is analyzed to determine two or more ports via which the MC packet is to be transmitted. It is determined that two or more pending read requests are to read packet data from a particular memory location in the packet memory. In response to determining that the two or more pending read requests are to read packet data from the particular memory location, the packet data is read a single time from the particular memory location. Respective instances of the packet data read from the particular memory location are provided to respective two or more read client devices for subsequent transmission of the packet data via the two or more ports determined by the packet processor.

Abstract: Packet data corresponding to a multicast (MC) packet received by a network device is stored in a packet memory. A header of the MC packet is analyzed to determine two or more ports via which the MC packet is to be transmitted. It is determined that two or more pending read requests are to read packet data from a particular memory location in the packet memory. In response to determining that the two or more pending read requests are to read packet data from the particular memory location, the packet data is read a single time from the particular memory location. Respective instances of the packet data read from the particular memory location are provided to respective two or more read client devices for subsequent transmission of the packet data via the two or more ports determined by the packet processor.

Abstract: A network device is described. The network device includes a plurality of ingress interfaces, a plurality of memory units configured to store packets received at the plurality of ingress interfaces, a first pool of memory access tokens, and one or more integrated circuits that implement a memory controller. The memory access tokens correspond to respective memory units and are distinct within the first pool. The memory controller is configured to selectively assign at least one individual memory access token to the ingress interfaces to govern write access to the memory units. The ingress interfaces write packets to memory units identified by the corresponding assigned memory access tokens. The network controller is configured to reassign a first memory access token from a first ingress interface to a second ingress interface between consecutive write commands from the first ingress interface based on a write access scheme to access non-sequential memory units.

Abstract: A network device is described. The network device includes a plurality of ingress interfaces, a plurality of memory units configured to store packets received at the plurality of ingress interfaces, a first pool of memory access tokens, and one or more integrated circuits that implement a memory controller. The memory access tokens correspond to respective memory units and are distinct within the first pool. The memory controller is configured to selectively assign at least one individual memory access token to the ingress interfaces to govern write access to the memory units. The ingress interfaces write packets to memory units identified by the corresponding assigned memory access tokens. The network controller is configured to reassign a first memory access token from a first ingress interface to a second ingress interface between consecutive write commands from the first ingress interface based on a write access scheme to access non-sequential memory units.

Abstract: Packet data corresponding to a multicast (MC) packet received by a network device is stored in a packet memory. A header of the MC packet is analyzed to determine two or more ports via which the MC packet is to be transmitted. It is determined that two or more pending read requests are to read packet data from a particular memory location in the packet memory. In response to determining that the two or more pending read requests are to read packet data from the particular memory location, the packet data is read a single time from the particular memory location. Respective instances of the packet data read from the particular memory location are provided to respective two or more read client devices for subsequent transmission of the packet data via the two or more ports determined by the packet processor.