Abstract: One aspect of the present disclosure relates to a method for operating an amplifier, the amplifier including a variable resistor coupled between a source of a first input transistor and a source of a second input transistors, and a variable capacitor coupled between the source of the first input transistor and the source of the second input transistor. The method includes adjusting a resistance of the variable resistor to adjust a low-frequency gain of the amplifier, and adjusting a capacitance of the variable capacitor in an opposite direction as the adjustment to the resistance of the variable resistor.

Abstract: One aspect of the present disclosure relates to a method for operating an amplifier, the amplifier including a variable resistor coupled between a source of a first input transistor and a source of a second input transistors, and a variable capacitor coupled between the source of the first input transistor and the source of the second input transistor. The method includes adjusting a resistance of the variable resistor to adjust a low-frequency gain of the amplifier, and adjusting a capacitance of the variable capacitor in an opposite direction as the adjustment to the resistance of the variable resistor.

Abstract: A method according to one embodiment includes receiving an increment signal at a first integrator when a second integrator overflows; receiving a decrement signal at the first integrator when the second integrator underflows; and incrementing or decrementing a gain applied to an analog signal based on receipt of the increment or decrement signal. A system according to one embodiment includes a first integrator configured to cause incrementing of a gain applied to an analog signal based on receipt of an increment signal when a second integrator overflows, the first integrator being configured to cause decrementing of the gain applied to the analog signal based on receipt of a decrement signal when the second integrator underflows; and the second integrator.

Abstract: A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first gain control circuit coupled to the variable gain amplifier for controlling the gain of the analog signal; an analog to digital converter for converting the analog signal to a digital signal; a first gain error generation circuit for generating a first gain error signal based on an output of the analog to digital converter, the first gain error signal or derivative thereof being received by the first gain control circuit; and a second gain error generation circuit for generating a second gain error signal based on the digital signal, the second gain error signal or derivative thereof being received by the first gain control circuit, wherein the first gain control circuit uses at least one of the gain error signals to control the gain of the analog signal.

Abstract: A method according to one embodiment includes receiving an increment signal at a first integrator when a second integrator overflows; receiving a decrement signal at the first integrator when the second integrator underflows; and incrementing or decrementing a gain applied to an analog signal based on receipt of the increment or decrement signal. A system according to one embodiment includes a first integrator configured to cause incrementing of a gain applied to an analog signal based on receipt of an increment signal when a second integrator overflows, the first integrator being configured to cause decrementing of the gain applied to the analog signal based on receipt of a decrement signal when the second integrator underflows; and the second integrator.

Abstract: A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first integrator coupled to the variable gain amplifier for controlling the gain of the analog signal; a second integrator generating control signals for controlling functions of the first integrator; a serializer for serializing the control signals; and a deserializer coupled to the serializer for deserializing the control signals and passing the deserialized control signals to the first integrator.

Abstract: A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first gain control circuit coupled to the variable gain amplifier for controlling the gain of the analog signal; an analog to digital converter for converting the analog signal to a digital signal; a first gain error generation circuit for generating a first gain error signal based on an output of the analog to digital converter, the first gain error signal or derivative thereof being received by the first gain control circuit; and a second gain error generation circuit for generating a second gain error signal based on the digital signal, the second gain error signal or derivative thereof being received by the first gain control circuit, wherein the first gain control circuit uses at least one of the gain error signals to control the gain of the analog signal.

Abstract: A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first gain control circuit coupled to the variable gain amplifier for controlling the gain of the analog signal; an analog to digital converter for converting the analog signal to a digital signal; a first gain error generation circuit for generating a first gain error signal based on an output of the analog to digital converter, the first gain error signal or derivative thereof being received by the first gain control circuit; and a second gain error generation circuit for generating a second gain error signal based on the digital signal, the second gain error signal or derivative thereof being received by the first gain control circuit, wherein the first gain control circuit uses at least one of the gain error signals to control the gain of the analog signals.

Abstract: A method according to one embodiment includes generating a first gain error, comprising: receiving an output of an equalizer; and comparing a magnitude of the output to a saturation threshold level; if the output is higher than the saturation threshold level, generating a first gain error. The method further including generating at least one of a second and a third gain error, wherein generating the second gain error comprises: using either a slicer or a trellis for generating the second gain error, wherein the slicer generates a gain error based on an output of an interpolator, wherein the trellis generates a gain error based on an output of a maximum likelihood detector; wherein generating the third gain error comprises: receiving an output of an equalizer; generating a threshold qualified peak from the equalizer output and a tracking threshold level; comparing the threshold qualified peak to a second threshold; and generating a third gain error based on the comparison.

Abstract: A method according to one embodiment includes generating a first gain error, comprising: receiving an output of an equalizer; and comparing a magnitude of the output to a saturation threshold level; if the output is higher than the saturation threshold level, generating a first gain error. The method further including generating at least one of a second and a third gain error, wherein generating the second gain error comprises: using either a slicer or a trellis for generating the second gain error, wherein the slicer generates a gain error based on an output of an interpolator, wherein the trellis generates a gain error based on an output of a maximum likelihood detector; wherein generating the third gain error comprises: receiving an output of an equalizer; generating a threshold qualified peak from the equalizer output and a tracking threshold level; comparing the threshold qualified peak to a second threshold; and generating a third gain error based on the comparison.

Abstract: A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first gain control circuit coupled to the variable gain amplifier for controlling the gain of the analog signal; an analog to digital converter for converting the analog signal to a digital signal; a first gain error generation circuit for generating a first gain error signal based on an output of the analog to digital converter, the first gain error signal or derivative thereof being received by the first gain control circuit; and a second gain error generation circuit for generating a second gain error signal based on the digital signal, the second gain error signal or derivative thereof being received by the first gain control circuit, wherein the first gain control circuit uses at least one of the gain error signals to control the gain of the analog signals.

Abstract: A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first integrator coupled to the variable gain amplifier for controlling the gain of the analog signal; a second integrator generating control signals for controlling functions of the first integrator; a serializer for serializing the control signals; and a deserializer coupled to the serializer for deserializing the control signals and passing the deserialized control signals to the first integrator.

Abstract: Provided are techniques for determining a reel motor angle. An estimate of an interval to degrees translation factor that represents a measurement angle interval divided by a first pulse count is calculated, wherein the first pulse count represents format transitions counted during an angular measurement interval. A reel motor angle is determined using the estimate by: receiving an indication that a rotating reference point has crossed a stationary reference point, wherein the indication is recognized as indicating that an angle between a motor rotor and a motor stator is a reference angle; determining a second pulse count, wherein the second pulse count represents format transitions counted since the indication was received to a given point in time; and at the given point in time, multiplying the second pulse count by the estimate to generate a first value and adding the reference angle to the first value to generate the reel motor angle.

Abstract: Provided are techniques for determining a reel motor angle. An estimate of an interval to degrees translation factor that represents a measurement angle interval divided by a first pulse count is calculated, wherein the first pulse count represents format transitions counted during an angular measurement interval. A reel motor angle is determined using the estimate by: receiving an indication that a rotating reference point has crossed a stationary reference point, wherein the indication is recognized as indicating that an angle between a motor rotor and a motor stator is a reference angle; determining a second pulse count, wherein the second pulse count represents format transitions counted since the indication was received to a given point in time; and at the given point in time, multiplying the second pulse count by the estimate to generate a first value and adding the reference angle to the first value to generate the reel motor angle.

Abstract: An apparatus, system, and method are disclosed for testing an analog to digital converter with a known analog signal applied. A first register module stores a first digitized instance of an analog signal. A second register module stores a second digitized instance of the analog signal. A difference module calculates the absolute difference between the first and second digitized instances. A bad code module identifies an erroneous digitized instance wherein the absolute difference is greater than a limit value. In one embodiment, a counter module counts the erroneous digitized instance. A test system may identify a failed analog to digital converter if the erroneous digitized instance count is greater than a specified target value.