Patents by Inventor Jacob Lorien Moilanen
Jacob Lorien Moilanen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8365172Abstract: A computer implemented method, data processing system, and computer program product for dynamically scheduling algorithms in a pipeline which operate on a stream of data. The illustrative embodiments determine a computational cost of each algorithm in a plurality of algorithms in a pipeline. The plurality of algorithms in the pipeline processes an incoming data stream in a first sequential algorithm order. The illustrative embodiments reorder the plurality of algorithms in the pipeline to form a second sequential algorithm order based on the computational cost of each algorithm. The plurality of algorithms may then be executed in the second sequential algorithm order. When the illustrative embodiments assign a spare processing unit to an algorithm at an end of the pipeline, the computational cost of each algorithm in the plurality of algorithms in the pipeline is redetermined.Type: GrantFiled: May 7, 2008Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Nathan D. Fontenot, Jacob Lorien Moilanen, Joel Howard Schopp, Michael Thomas Strosaker
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Patent number: 8307367Abstract: Partition migrations are scheduled between virtual partitions of a virtually partitioned data processing system. The virtually partitioned data processing system is a tickless system in which a periodic timer interrupt is not guaranteed to be sent to the processor at a defined time interval. A request is received for a partition migration. Gaps between scheduled timer interrupts are identified. The partition migration is then scheduled to occur within the largest gap.Type: GrantFiled: March 5, 2009Date of Patent: November 6, 2012Assignee: International Business Machines CorporationInventors: Manish Ahuja, Nathan D. Fontenot, Jacob Lorien Moilanen, Joel Howard Schopp, Michael Thomas Strosaker
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Patent number: 8166480Abstract: Illustrative embodiments provide a computer implemented method, a data processing system and a computer program product for lock contention reduction. In one illustrative embodiment, the computer implemented method provides a lock to an active thread, increments a lock counter, receives a request to de-schedule the active thread, and determines whether the lock is held by the active thread. The computer implemented method, responsive to a determination that the lock is held by the active thread, adds a first pre-determined amount to a time slice of the active thread.Type: GrantFiled: July 29, 2008Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Nathan D. Fontenot, Jacob Lorien Moilanen, Joel Howard Schopp, Michael Thomas Strosaker, Mark Wayne VanderWiele
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Patent number: 7958381Abstract: A method, system, and computer usable program product for energy conservation in multipath data communications are provided in the illustrative embodiments. A current utilization of each of several of I/O devices is determined. A violation determination is made whether an I/O device from the several I/O devices can be powered down without violating a rule. The I/O device is powered down responsive to the violation determination being false. A powering up determination may be made whether an additional I/O device is needed in a multipath I/O configuration. The I/O device may be located, powered up, and made available for multipath I/O configuration. A latency determination may be made whether a latency time of the I/O device can elapse before the time when the additional I/O device is needed. The powering on may occur no later than the latency time before the time the additional I/O device is needed.Type: GrantFiled: June 27, 2008Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Nathan Fontenot, Jacob Lorien Moilanen, Joel Howard Schopp, Michael Thomas Strosaker
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Publication number: 20100229181Abstract: Partition migrations are scheduled between virtual partitions of a virtually partitioned data processing system. The virtually partitioned data processing system is a tickless system in which a periodic timer interrupt is not guaranteed to be sent to the processor at a defined time interval. A request is received for a partition migration. Gaps between scheduled timer interrupts are identified. The partition migration is then scheduled to occur within the largest gap.Type: ApplicationFiled: March 5, 2009Publication date: September 9, 2010Applicant: International Business Machines CorporationInventors: Manish Ahuja, Nathan D. Fontenot, Jacob Lorien Moilanen, Joel Howard Schopp, Michael Thomas Strosaker
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Patent number: 7669204Abstract: Methods, systems, and media are disclosed for autonomic system tuning of simultaneous multithreading (“SMT”). In one embodiment, the method for autonomic tuning of at least one SMT setting for an optimized processing, such as via throughput, latency, and power consumption, of a workload on a computer system includes calling, by a kernel, an SMT scheduler having at least one hook into a genetic library. Further, the method includes obtaining, by the SMT scheduler through the at least one hook, genetic data from the genetic library for the optimized processing of the workload. Further still, the method includes tuning, by the SMT scheduler and based on the obtaining, the at least one SMT setting for at least one cpu of the computer system.Type: GrantFiled: October 14, 2004Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: Jacob Lorien Moilanen, Joel Howard Schopp
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Publication number: 20100031269Abstract: Illustrative embodiments provide a computer implemented method, a data processing system and a computer program product for lock contention reduction. In one illustrative embodiment, the computer implemented method provides a lock to an active thread, increments a lock counter, receives a request to de-schedule the active thread, and determines whether the lock is held by the active thread. The computer implemented method, responsive to a determination that the lock is held by the active thread, adds a first pre-determined amount to a time slice of the active thread.Type: ApplicationFiled: July 29, 2008Publication date: February 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan D. Fontenot, Jacob Lorien Moilanen, Joel Howard Schopp, Michael Thomas Strosaker, Mark Wayne VanderWiele
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Publication number: 20090327779Abstract: A method, system, and computer usable program product for energy conservation in multipath data communications are provided in the illustrative embodiments. A current utilization of each of several of I/O devices is determined. A violation determination is made whether an I/O device from the several I/O devices can be powered down without violating a rule. The I/O device is powered down responsive to the violation determination being false. A powering up determination may be made whether an additional I/O device is needed in a multipath I/O configuration. The I/O device may be located, powered up, and made available for multipath I/O configuration. A latency determination may be made whether a latency time of the I/O device can elapse before the time when the additional I/O device is needed. The powering on may occur no later than the latency time before the time the additional I/O device is needed.Type: ApplicationFiled: June 27, 2008Publication date: December 31, 2009Applicant: International Business Machines CorporationInventors: Nathan Fontenot, Jacob Lorien Moilanen, Joel Howard Schopp, Michael Thomas Strosaker
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Publication number: 20090282217Abstract: A computer implemented method, data processing system, and computer program product for dynamically scheduling algorithms in a pipeline which operate on a stream of data. The illustrative embodiments determine a computational cost of each algorithm in a plurality of algorithms in a pipeline. The plurality of algorithms in the pipeline processes an incoming data stream in a first sequential algorithm order. The illustrative embodiments reorder the plurality of algorithms in the pipeline to form a second sequential algorithm order based on the computational cost of each algorithm. The plurality of algorithms may then be executed in the second sequential algorithm order. When the illustrative embodiments assign a spare processing unit to an algorithm at an end of the pipeline, the computational cost of each algorithm in the plurality of algorithms in the pipeline is redetermined.Type: ApplicationFiled: May 7, 2008Publication date: November 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan D. Fontenot, Jacob Lorien Moilanen, Joel Howard Schopp, Michael Thomas Strosaker
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Patent number: 7571286Abstract: A computer implemented method, data processing system, and computer program product for reducing memory traffic via detection and tracking of temporally silent stores. When a memory store, comprising an address and a data value, to a cache is detected, a determination is made that a cache line in the cache contains a same address as the address in the memory store. A determination is then made that a tentative cache line invalidate signal for the cache line was previously sent to other data processing systems in the network to tentatively invalidate the cache line. If the memory store is a temporally silent store, a cache line revalidate signal is sent to the other data processing systems to clear the tentative invalidate signal for the cache line.Type: GrantFiled: August 24, 2006Date of Patent: August 4, 2009Assignee: International Business Machines CorporationInventors: Nathan D. Fontenot, Jacob Lorien Moilanen, Joel Howard Schopp, Michael Thomas Strosaker
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Patent number: 7493419Abstract: A computer implemented method in a data processing system for fingerprinting input/output workloads for input/output schedulers. Requests are identified in a workload for an input/output scheduler. Each request is classified to form a set of classifications. Whether an action is needed is determined based on the set of classifications. If the action is needed, the action is initiated.Type: GrantFiled: December 13, 2005Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventor: Jacob Lorien Moilanen
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Publication number: 20080177682Abstract: Methods, systems, and media are disclosed for autonomic system tuning of simultaneous multithreading (“SMT”). In one embodiment, the method for autonomic tuning of at least one SMT setting for an optimized processing, such as via throughput, latency, and power consumption, of a workload on a computer system includes calling, by a kernel, an SMT scheduler having at least one hook into a genetic library. Further, the method includes obtaining, by the SMT scheduler through the at least one hook, genetic data from the genetic library for the optimized processing of the workload. Further still, the method includes tuning, by the SMT scheduler and based on the obtaining, the at least one SMT setting for at least one cpu of the computer system.Type: ApplicationFiled: March 26, 2008Publication date: July 24, 2008Inventors: Jacob Lorien Moilanen, Joel Howard Schopp
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Publication number: 20080114971Abstract: A computer implemented method, apparatus, and computer program product for preserving branch history data. The process creates a branch history table in a buffer. The process saves an address for each executed branch instruction that occurs during execution of code in the branch history table to form branch history data. In response to detecting an exception, the process saves the branch history data to an allocated memory space to form a branch history snapshot.Type: ApplicationFiled: November 14, 2006Publication date: May 15, 2008Inventors: Nathan D. Fontenot, Jacob Lorien Moilanen, Joel Howard Schopp, Michael Thomas Strosaker
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Publication number: 20080086465Abstract: A computer implemented method, data processing system, and computer program product for establishing document relevance by semantic network density. When a search query is received, one or more semantic networks are identified which contain nodes matching one or more terms in the search query. An edge density is determined for each node matching a term in the search query. A relevancy score is then calculated for each of the one or more semantic networks based on the edge densities of the nodes matching a term in the search query. Based on the relevancy score, the relevancy to the search query of a document associated with the one or more semantic networks may then be determined.Type: ApplicationFiled: October 9, 2006Publication date: April 10, 2008Inventors: Nathan D. Fontenot, Jacob Lorien Moilanen, Joel Howard Schoop, Michael Thomas Strosaker
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Publication number: 20080052469Abstract: A computer implemented method, data processing system, and computer program product for reducing memory traffic via detection and tracking of temporally silent stores. When a memory store, comprising an address and a data value, to a cache is detected, a determination is made that a cache line in the cache contains a same address as the address in the memory store. A determination is then made that a tentative cache line invalidate signal for the cache line was previously sent to other data processing systems in the network to tentatively invalidate the cache line. If the memory store is a temporally silent store, a cache line revalidate signal is sent to the other data processing systems to clear the tentative invalidate signal for the cache line.Type: ApplicationFiled: August 24, 2006Publication date: February 28, 2008Inventors: Nathan D. Fontenot, Jacob Lorien Moilanen, Joel Howard Schopp, Michael Thomas Strosaker