Abstract: Aspects of the subject disclosure may include, for example, a track-and-hold sampling circuit, having: a duty-cycle limiter that generates a clock signal having a duty cycle that is less than 100% from three out of four clock signals; and a sampling circuit comprising complementary positive and negative input gates that track and sample data input signals, wherein the sampling circuit generates sampled data signals, wherein the complementary positive and negative input gates are coupled to the clock signal. Other embodiments are disclosed.

Abstract: Aspects of the subject disclosure may include, for example, a multiphase clock generator having a plurality of digital phase interpolators each configured to create a generated clock signal according to an applied digital code, wherein a first digital code applied to a first digital phase interpolator and a second digital code applied to a second digital phase interpolator are chosen in a less precise range such that a first generated clock signal output by the first digital phase interpolator is as close to an ideal phase separation from a second generated clock signal output by the second digital phase interpolator, and wherein additional codes are applied to other digital phase interpolators in a more precise range to create generated clock signals having a deviation from an ideal separation from the first generated clock signal or the second generated clock signal that is less than a linear resolution of the applied digital code. Other embodiments are disclosed.

Abstract: Aspects of the subject disclosure may include, for example, a multiphase clock generator having a plurality of digital phase interpolators each configured to create a generated clock signal according to an applied digital code, wherein a first digital code applied to a first digital phase interpolator and a second digital code applied to a second digital phase interpolator are chosen in a less precise range such that a first generated clock signal output by the first digital phase interpolator is as close to an ideal phase separation from a second generated clock signal output by the second digital phase interpolator, and wherein additional codes are applied to other digital phase interpolators in a more precise range to create generated clock signals having a deviation from an ideal separation from the first generated clock signal or the second generated clock signal that is less than a linear resolution of the applied digital code. Other embodiments are disclosed.

Abstract: Aspects of the subject disclosure may include, for example, an inner clock generation circuit, including: a selectable frequency divider having: a ring of tri-state inverters; a reset gate on an output of each tri-state inverter in the ring; and a reset circuit comprising one or more selectable flip-flops; and a duty-cycle limiter that generates clock signals having a 25% duty cycle from three out of four quadrature clock signals. Other embodiments are disclosed.

Abstract: Aspects of the subject disclosure may include, for example, implementing a first stage including a first number of phase rotators in parallel generating respective clock phases offset by a fixed amount; a second stage including a second number of phase rotators receiving outputs from the first number of phase rotators of the first stage, the second stage outputting a first weighted sum of respective clock phases generated by the second number of phase rotators. The subject disclosure further includes the second number of phase rotators being less than the first number of phase rotators, and a total number of bits dedicated to phase selection being split across the first stage and the second stage. Other embodiments are disclosed.

Abstract: Aspects of the subject disclosure may include, for example, implementing a first stage including a first number of phase rotators in parallel generating respective clock phases offset by a fixed amount; a second stage including a second number of phase rotators receiving outputs from the first number of phase rotators of the first stage, the second stage outputting a first weighted sum of respective clock phases generated by the second number of phase rotators. The subject disclosure further includes the second number of phase rotators being less than the first number of phase rotators, and a total number of bits dedicated to phase selection being split across the first stage and the second stage. Other embodiments are disclosed.

Abstract: Aspects of the subject disclosure may include, for example, implementing a first stage including a first number of phase rotators in parallel generating respective clock phases offset by a fixed amount; a second stage including a second number of phase rotators receiving outputs from the first number of phase rotators of the first stage, the second stage outputting a first weighted sum of respective clock phases generated by the second number of phase rotators. The subject disclosure further includes the second number of phase rotators being less than the first number of phase rotators, and a total number of bits dedicated to phase selection being split across the first stage and the second stage. Other embodiments are disclosed.

Abstract: A decision feedback equalizer (DFE) comprises four charge-steering (CS) primary latches and four primary taps. Two of the four CS primary latches are driven by complementary in-phase quarter-rate clocks and the other two of the four CS primary latches are driven by complementary quadrature quarter-rate clocks. No element of the DFE is driven by any half-rate clocks. In some implementations, each of the primary latches including a respective differential pair of n-channel output transistors and each primary tap includes a respective differential pair of p-channel input transistors connected via their gate nodes to a respective one of the four CS primary latches. In other implementations, each of the primary latches including a respective differential pair of p-channel input transistors and each primary tap includes a respective differential pair of n-channel output transistors connected via their gate nodes to a respective one of the four CS primary latches.

Abstract: A decision feedback equalizer (DFE) comprises two charge-steering (CS) input latches driven by complementary ½-rate clocks, two pairs of CS primary latches, and two pairs of taps. The primary latches are driven by ¼-rate clocks. In a first aspect, each one of the input latches and the primary latches includes a respective differential pair of n-channel output transistors, and each tap includes a respective differential pair of p-channel input transistors. In a second aspect, each one of the input latches and the primary latches includes a respective differential pair of p-channel input transistors, and each tap includes a respective differential pair of n-channel output transistors. In some implementations, no element of any one of the taps is driven by any ½-rate clock. In some implementations, every switch of at least one of the taps is driven by one of the ¼-rate clocks.