Abstract: A method fabricating at least one universal substrate from a batch product. The method includes steps of: providing a preform having a predetermined profile; wrapping a plurality of conductors about an outer surface of the preform; injecting a nonconductive matrix between conductors of the plurality of conductors, wherein the nonconductive matrix permeates between interstitial spaces of the plurality of conductors to isolate some conductors of the plurality of conductors from one another; forming the batch product that includes the plurality of conductors and the nonconductive matrix; and wafering at least one section of the batch product to form the at least one universal substrate. The plurality of conductors of the at least one universal substrate defines a first connection surface, a second connection surface opposite to the first connection surface, and a plurality of conductive pathways defined between the first connection surface and the second connection surface.

Abstract: Integrated capacitor structures are described. In an example, an interconnect structure includes a first layer of conductive material and a second layer of conductive material. The first layer includes a first horizontal portion having a first opening and extending along a first horizontal plane, and a first vertical portion. The second layer includes a second horizontal portion having a second opening and extending along a second horizontal plane, and a second vertical portion. The interconnect structure also includes a dielectric extending along a third horizontal plane between the first and second horizontal portions, and having one or more openings. The first vertical component extends upward from the first horizontal portion, through one opening in the dielectric and the second opening of second layer, and the second vertical component extends downward from the second horizontal portion, through another opening in the dielectric and the first opening of first layer.

Abstract: An integrated circuit structure includes (i) a first layer including a first metal, (ii) a second layer above and in contact with the first layer, the second layer including a resistive material, and (iii) a third layer above and in contact with the second layer, the third layer including a second metal. In an example, the resistive material is different from one or both the first metal and the second metal. An interconnect component is above and in contact with the second layer. In an example, the interconnect component is a solder bump or a solder ball. In an example, a resistivity of the resistive material of the second layer is at least 20%, or at least 50% greater than a resistivity of each of the first and third layers. In an example, the resistive material includes a third metal different from the first and second metals and/or a metalloid.

Abstract: A microelectronic component includes a substrate having at least one electrical pad, a resilient material on the substrate, and a conductive element on or in the resilient material and coupled to the at least one conductive pad. The resilient material may include, for instance, a compressible polymer. The conductive elements configured to be placed in contact with at least one test probe, where the resilient material is configured to be compressed by the at least one electrical probe into a deformed shape and where the resilient material is configured to return from the deformed shape to a non-deformed shape subsequent to a removal of the conductive element from contact with the at least one electrical probe.

Abstract: An integrated circuit (IC) package comprises a substrate having an outer portion close to the perimeter of the substrate, an inner portion surrounded by the outer portion, and an upper surface incorporating a wiring layer for the bonding of a semiconducting die (e.g., via its bottom face). The IC package includes a metallic or otherwise thermally conductive heat spreader thermally bonded on an inner surface of a boss on its bottom side to the top surface of the semiconducting die, and extending on its top surface to the edges of the substrate to maximize heat dissipation from the die. The boss extends toward the semiconducting die and is thermally coupled to the top face of the semiconducting die.

Abstract: A system and method. The system may include an integrated circuit (IC) die. The IC die may have two faces and sides. The system may further include mold material. The mold material may surround at least the sides of the IC die. The IC die may be mechanically interlocked with the mold material.

Abstract: A system and method. The system may include an integrated circuit (IC) die having two faces and sides. The system may further include mold material surrounding at least the sides of the IC die. The system may further include a redistribution layer and signal pads. The redistribution layer may be positioned between (a) the signal pads and (b) the mold material and the IC die. The redistribution layer may have conductive paths at least connecting the IC die and at least some of the signal pads. A surface of the mold material may abut the redistribution layer. The surface of the mold material may include at least one recessed area having at least one conductive feature connected to at least one of the conductive paths or the IC die.

Abstract: A system and method includes pre-warping a mask to induce strain when affixed to a substrate and ensure positive contact between the mask and the substrate during all phases of deposition. A film is applied to the mask at a rate sufficient to impart stress to the film faster than such stress can be released. Depending on the features defined by the mask, the pre-warping may be concentric, linear along one axis, or complex along a plurality of axes.

Abstract: A system and method. The system may include an integrated circuit (IC) die. The IC die may have two faces and sides. The system may further include mold material. The mold material may surround at least the sides of the IC die. The IC die may be mechanically interlocked with the mold material.

Abstract: A system and method. The system may include an integrated circuit (IC) die having two faces and sides. The system may further include mold material surrounding at least the sides of the IC die. The system may further include a redistribution layer and signal pads. The redistribution layer may be positioned between (a) the signal pads and (b) the mold material and the IC die. The redistribution layer may have conductive paths at least connecting the IC die and at least some of the signal pads. A a surface of the mold material may abut the redistribution layer. The surface of the mold material may include at least one recessed area having at least one conductive feature connected to at least one of the conductive paths or the IC die.

Abstract: An integrated circuit (IC) package incorporating controlled induced warping is disclosed. The IC package includes an electronic substrate having an active side upon which semiconducting dies and functional circuits have been lithographed or otherwise fabricated, leading to an inherent warping in the direction of the active side. One or more corrective layers may be deposited to the opposing, or inactive, side of the semiconducting die via electroplating in order to induce corrective warping of the electronic substrate back toward the horizontal (e.g., in the direction of the inactive side) to a desired degree.

Abstract: An integrated circuit (IC) package incorporating controlled induced warping is disclosed. The IC package includes an electronic substrate having an active side upon which semiconducting dies and functional circuits have been lithographed or otherwise fabricated, leading to an inherent warping in the direction of the active side. One or more corrective layers may be deposited to the opposing, or inactive, side of the semiconducting die via thin film deposition (TFD) instrumentation and techniques in order to induce corrective warping of the electronic substrate back toward the horizontal (e.g., in the direction of the inactive side) to a desired degree.

Abstract: A system and method includes pre-warping a mask to induce strain when affixed to a substrate and ensure positive contact between the mask and the substrate during all phases of deposition. A film is applied to the mask at a rate sufficient to impart stress to the film faster than such stress can be released. Depending on the features defined by the mask, the pre-warping may be concentric, linear along one axis, or complex along a plurality of axes.

Abstract: An integrated circuit (IC) package incorporating controlled induced warping is disclosed. The IC package includes an electronic substrate having an active side upon which semiconducting dies and functional circuits have been lithographed or otherwise fabricated, leading to an inherent warping in the direction of the active side. One or more corrective layers may be deposited to the opposing, or inactive, side of the semiconducting die via electroplating in order to induce corrective warping of the electronic substrate back toward the horizontal (e.g., in the direction of the inactive side) to a desired degree.

Abstract: An integrated circuit (IC) package incorporating controlled induced warping is disclosed. The IC package includes an electronic substrate having an active side upon which semiconducting dies and functional circuits have been lithographed or otherwise fabricated, leading to an inherent warping in the direction of the active side. One or more corrective layers may be deposited to the opposing, or inactive, side of the semiconducting die via thin film deposition (TFD) instrumentation and techniques in order to induce corrective warping of the electronic substrate back toward the horizontal (e.g., in the direction of the inactive side) to a desired degree.