Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a row decoder configured to configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections. The row decoder may be further configured to stop an access operation associated with the prime row from proceeding based on a comparison of subset of match signals from either the first or second pluralities of row sections.

Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a row decoder configured to configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections. The row decoder may be further configured to stop an access operation associated with the prime row from proceeding based on a comparison of subset of match signals from either the first or second pluralities of row sections.

Abstract: A variable stiffness actuator comprises a flexure plate which comprises a first cantilevered beam that extends inwards from an outer periphery of the flexure plate. A housing and the flexure plate rotatable about a common joint axis. A first contactor is pivotably secured at a revolute joint to the housing. The first contactor rotates about the revolute joint at a first rotation axis. The first rotation axis offset on the housing from the joint axis. The first contactor engages the first cantilevered beam at a variable angle about the rotation axis to adjust a stiffness of a mechanical connection between the flexure plate and the housing.

Abstract: A variable stiffness actuator comprises a flexure plate which comprises a first cantilevered beam that extends inwards from an outer periphery of the flexure plate. A housing and the flexure plate rotatable about a common joint axis. A first contactor is pivotably secured at a revolute joint to the housing. The first contactor rotates about the revolute joint at a first rotation axis. The first rotation axis offset on the housing from the joint axis. The first contactor engages the first cantilevered beam at a variable angle about the rotation axis to adjust a stiffness of a mechanical connection between the flexure plate and the housing.