Abstract: A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+ layer on the P layer is provided. A pattern of U-shaped openings is formed in the body through to the P substrate by the reactively ion etching technique. This pattern of openings is filled with an insulator material, such as silicon dioxide. A conductive layer of N+ doped polycrystalline silicon is deposited on the bare surface of this silicon body. Openings are formed in the polycrystalline silicon over the silicon dioxide filled openings. A silicon dioxide layer is then grown by, for example, thermal oxidation over the polycrystalline silicon layer. Reactively ion etching is used to produce substantially U-shaped openings through the layers over the P substrate and into the P substrate to substantially bisect the regions of monocrystalline silicon.

Abstract: A method for forming an insulator between conductive layers, such as highly doped polycrystalline silicon, that involves first forming a conductive layer of, for example, polycrystalline silicon on a silicon body having substantially horizontal and substantially vertical surfaces. A conformal insulator layer is formed on the substantially horizontal and substantially horizontal and vertical surfaces. Reactive ion etching removes the insulator from the horizontal layer and provides a narrow dimensioned insulator on the vertical surfaces silicon body. Another conductive layer, which may be polycrystalline silicon, is formed over the insulator. The vertical layer dimension is adjusted depending upon the original thickness of the conformal insulator layer applied.

Abstract: A method for forming diffusions having narrow, for example, submicrometer dimensions in a silicon body which involves forming insulator regions on a silicon body, which insulator regions have substantially horizontal surfaces and substantially vertical surfaces. A layer having a desired dopant concentration is formed thereon, both on the substantially horizontal surfaces and the substantially vertical surfaces. Reactive ion etching of the layer acts to substantially remove only the horizontal layer and provides a narrow dimensioned layer having a desired dopant concentration in the substantially vertical surfaces. Heating of the body at a suitable temperature is accomplished so as to produce the movement of the dopant into the silicon body by diffusion to form diffusions having narrow, such as submicrometer dimensions, therein.

Abstract: A method for forming a narrow, such as a submicrometer, dimensioned mask opening on a silicon body involving forming a first insulator region having substantially a horizontal surface and a substantially vertical surface. A second insulator is applied on both the horizontal surface and substantially vertical surfaces. The second insulator is composed of a material different from that of the first insulator layer. Reactive ion etching of the second layer removes the horizontal layer and provides a narrow dimensioned second insulator region on the silicon body. The surface of the silicon body is then thermally oxidized. The narrow dimensioned second insulator region is removed to form a narrow dimensioned mask opening.

Abstract: A method for forming a fully-enclosed air isolation structure which comprises etching a pattern of cavities extending from one surface of a silicon substrate into the substrate to laterally surround and electrically isolate said plurality of substrate pockets, and then forming a first layer of silicon dioxide on said first substrate surface. Next, a planar second layer comprising silicon dioxide is formed over a second silicon substrate, after which this planar layer is fused to said silicon dioxide layer to thereby fully enclose said cavities. Then, the second silicon substrate is removed.

Abstract: An integrated circuit member structure comprising a semiconductor substrate having formed therein a pattern of cavities extending from one surface of the substrate into the substrate and fully enclosed within said member, a plurality of pockets of semiconductor material extending from said substrate laterally surrounded and electrically insulated by said cavities and a planar layer of electrically insulative material on said surface.

Abstract: Disclosed is a dynamic memory cell storing digital information, particularly adapted for integrated semiconductor circuit fabrication. The circuit configuration has a bipolar transistor with information storage preferrably in the capacitance of the junctions, and a field effect transistor (FET) for selectively injecting charge into the capacitances. In integrated form, isolation is required only between columns of cells, a buried subcollector forming a common sense line for the entire column, while each of the base regions (also used as a first controlled region of the FET) requires no external contact at all. A further impurity region formed into each column of cells forms a second region of the FET and can be used as a bit line for the entire column. In one embodiment, separate contacts are provided for each of the emitter regions and each of the FET gate regions, while in another embodiment, only a single contact to both of the emitter region and FET gate region of each cell is required.

Abstract: An improved composite channel field effect transistor and method of fabrication, which exhibits high density characteristics and yields high performance with less sensivity to threshold shift due to hot electrons when operated at high source to drain voltage levels.

Abstract: An improved FET structure and method of making same is disclosed. The gate structure of the FET includes a phospho-silicate glass as the insulator and polysilicon as the gate conductor. A thin layer of silicon nitride is formed over the polysilicon and selectively etched so as to remain only over gate areas and other areas where it is desired to extend the polysilicon as a conductor. The unmasked polysilicon is oxidized to form the thick oxide surface coating. The disclosure also describes the use of oxide rings and epitaxial layers to reduce parasitic effects between adjacent FET devices in an integrated circuit.

Abstract: A beam-lead integrated circuit chip structure which comprises a semiconductor chip substrate having a passivated planar surface from which active and passive devices in the circuit extend into the substrate. A plurality of peripheral beam-leads interconnected with the chip devices extend beyond the periphery of the chip and a plurality of solder mounds having a lower melting point than said beam-leads extends from the surface of the chip to a point beyond the plane of the beam-leads.This chip structure permits a method of automatic alignment of said plurality of beam-leads with a corresponding plurality of beam-leads on a dielectric substrate which involves placing the chip on the substrate so that said plurality of solder mounds are respectively in registration with a plurality of corresponding solder-wettable land pads on said non-wettable dielectric substrate.

Abstract: A charge-coupled random access memory cell is formed in a semiconductor body divided into three adjacent regions. The first region has an impurity diffused therein and serves alternately as a source and a drain for charge carriers. The second or gate region has a threshold voltage determined by an impurity imparted thereto by either diffusion or ion implantation. The third or storage region has a lower threshold voltage than the gate region. A single unitary metal electrode extends in superimposed relation to the second and third regions. Upon the application of potentials to the first region and the electrode, charge carriers may be stored in or removed from the third region so as to write a "1" or a "0" in the cell.

Abstract: A beam-lead integrated circuit chip structure which comprises a semiconductor chip substrate having a passivated planar surface from which active and passive devices in the circuit extend into the substrate. A plurality of peripheral beam-leads interconnected with the chip devices extend beyond the periphery of the chip and a plurality of solder mounds having a lower melting point than said beam-leads extends from the surface of the chip to a point beyond the plane of the beam-leads.This chip structure permits a method of automatic alignment of said plurality of beam-leads with a corresponding plurality of beam-leads on a dielectric substrate which involves placing the chip on the substrate so that said plurality of solder mounds are respectively in registration with a plurality of corresponding solder-wettable land pads on said non-wettable dielectric substrate.

Abstract: In the fabrication of integrated circuits, a method is provided for forming dielectrically isolated regions in the silicon substrate comprising selectively etching recesses in a silicon substrate and thermally oxidizing the recessed portions of the silicon substrate to form regions of recessed silicon dioxide extending into the substrate. Then, a blanket introduction of impurities of opposite-type conductivity is made into the portions of the substrate remaining unoxidized, after which a layer of silicon of said opposite-type conductivity is epitaxially deposited on the substrate surface. Next, utilizing appropriate silicon nitride masking, recesses are etched into the silicon epitaxial layer in registration with the now buried regions of recessed silicon dioxide in the substrate.

Abstract: An improved FET structure and method of making same is disclosed. The gate structure of the FET includes a phospho-silicate glass as the insulator and polysilicon as the gate conductor. A thin layer of silicon nitride is formed over the polysilicon and selectively etched so as to remain only over gate areas and other areas where it is desired to extend the polysilicon as a conductor. The unmasked polysilicon is oxidized to form the thick oxide surface coating. The disclosure also describes the use of oxide rings and epitaxial layers to reduce parasitic effects between adjacent FET devices in an integrated circuit.