Abstract: A panel system includes a chassis holding one or more tray arrangements, which are each configured to receive one or more cassettes at two or more bays. The tray arrangements and cassettes cooperate to define a cassette sensor arrangement and a port occupancy sensor arrangement having separate interface points. The cassette sensor arrangement may include electronic memory storing physical layer information about the cassette. All active components of the port occupancy sensor arrangement are disposed on the tray while the electronic memories of the cassette sensor arrangement are stored on the cassettes.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. Chip enable circuits having control logic are configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. Chip enable circuits having control logic are configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. The memory further may include chip enable circuits having control logic configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. The memory further may include chip enable circuits having control logic configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

Abstract: Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively.

Abstract: Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively.

Abstract: Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively.