Abstract: In one embodiment a network device includes multiple interfaces including at least one egress interface, which is configured to transmit packets belonging to multiple flows to a packet data network, control circuitry configured to generate event-reporting data-items, each including flow and event-type information about a packet-related event occurring in the network device, a memory, and aggregation circuitry configured to aggregate data of at least some of the event-reporting data-items into aggregated-event-reporting data-items aggregated according to the flow and event-type information of the at least some event-reporting data-items, store the aggregated-event-reporting data-items in the memory, and forward one aggregated-event-reporting data-item of the aggregated-event-reporting data-items to a collector node, and purge the one aggregated-event-reporting data-item from the memory.

Abstract: In one embodiment a network device includes multiple interfaces including at least one egress interface, which is configured to transmit packets belonging to multiple flows to a packet data network, control circuitry configured to generate event-reporting data-items, each including flow and event-type information about a packet-related event occurring in the network device, a memory, and aggregation circuitry configured to aggregate data of at least some of the event-reporting data-items into aggregated-event-reporting data-items aggregated according to the flow and event-type information of the at least some event-reporting data-items, store the aggregated-event-reporting data-items in the memory, and forward one aggregated-event-reporting data-item of the aggregated-event-reporting data-items to a collector node, and purge the one aggregated-event-reporting dam-item from the memory.

Abstract: A network element connects over a network to a network node via a member link of a Multi-Chassis—Link Aggregation Link Group (MC-LAG), and further connects, using inter-peer ports, to peer network elements coupled to the network node via other MC-LAG member links. A processor of the network element is configured to receive from the network first packets destined to the network node, to receive via the inter-peer ports information indicative of second packets received from the network by the peer network elements that are destined to the network node, to select at least some of the first packets for transmission at an egress rate that jointly with egress rates of the peer network elements does not exceed a predefined MC-LAG maximal rate, based on the first packets and the information, and to transmit the selected first packets to the network node at the egress rate.

Abstract: A network element connects over a network to a network node via a member link of a Multi-Chassis—Link Aggregation Link Group (MC-LAG), and further connects, using inter-peer ports, to peer network elements coupled to the network node via other MC-LAG member links. A processor of the network element is configured to receive from the network first packets destined to the network node, to receive via the inter-peer ports information indicative of second packets received from the network by the peer network elements that are destined to the network node, to select at least some of the first packets for transmission at an egress rate that jointly with egress rates of the peer network elements does not exceed a predefined MC-LAG maximal rate, based on the first packets and the information, and to transmit the selected first packets to the network node at the egress rate.

Abstract: Packet flows received in a data network are assigned to respective entries of a database. During an accumulation interval byte counts of the assigned packet flows are accumulated in the respective database entries. The packet flows are classified as elephant flows when differences between the byte counts and a reference byte count exceed a threshold and are reported after expiration of the accumulation interval.

Abstract: Packet flows received in a data network are assigned to respective entries of a database. During an accumulation interval byte counts of the assigned packet flows are accumulated in the respective database entries. The packet flows are classified as elephant flows when differences between the byte counts and a reference byte count exceed a threshold and are reported after expiration of the accumulation interval.

Abstract: A method for fast and economic handling of overhead bytes of an incoming high order data stream to form a corresponding outgoing high order data stream, the method comprising a) presenting the incoming high order data stream as a plurality of N component data streams transmitted in parallel, b) providing a common overhead processing unit (COHPU) capable of handling overhead bytes of a single one of the component data streams, c) forwarding overhead bytes of the component data streams to the COHPU in a circular order, while keeping docketing (ID) information for each particular overhead byte; d) processing each of the overhead bytes in the COHPU, and e) modifying the N component data streams to obtain an outgoing high order data stream based on results of the processing and the ID information with respect to each of the processed overhead bytes.

Abstract: A binary tree-like structure for converting bit rates in a telecommunication system, comprising at least one cyclic generator (CG) adapted to present a higher bit rate called R1 substantially as a sum of two lower bit rates called R2 and R3 by cyclically producing, per n clocks of the bit rate R1, m first type signals as clocks of the bit rate R2 and (n?m) second type signals as clocks of the bit rate R3, where m and n are parameters of the CG and integers such, that m<n. The two lower bit rates R2 and R3, based on its parameters m and n, can be presented as follows: R2=mR1/n, R3=(n?m)R1/n. The higher bit rate R1 of a particular CG is either obtained from outside of the binary tree-like structure or constitutes a lower bit rate of another, upper range CG of the structure, while each of the lower bit rates R2 or R3 of a particular CG is either dispatched away from the structure or constitutes a higher bit rate of another, lower range CG of the structure.

Abstract: A method and a generator are described for high speed generation of an S-bit long pattern of a PRBS sequence to be periodically burst on to a bus of width S. The technique provides the calculation time being independent from the width S of the bus, and comprises calculation of all S bits of the PRBS pattern separately and in parallel by using previous PRBS patterns stored in a memory. For each bit to be generated, the generator performs a constant number N of logical operations require(by a polynomial defining the PRBS sequence.

Abstract: A method for fast and economic handling of overhead bytes of an incoming high order data stream to form a corresponding outgoing high order data stream, the method comprising a) presenting the incoming high order data stream as a plurality of N component data streams transmitted in parallel, b) providing a common overhead processing unit (COHPU) capable of handling overhead bytes of a single one of the component data streams, c) forwarding overhead bytes of the component data streams to the COHPU in a circular order, while keeping docketing (ID) information for each particular overhead byte; d) processing each of the overhead bytes in the COHPU, and e) modifying the N component data streams to obtain an outgoing high order data stream based on results of the processing and the ID information with respect to each of the processed overhead bytes.

Abstract: The invention discloses a cyclic generator of enabling/disabling signals (EG) adapted to convert an incoming data stream having a bit rate RI into an outgoing data stream having a bit rate R2, wherein R1≅mR2/n , m<n, m and n—integers being parameters of said EG selected to provide m enable signals per n clocks of the bit rate R2, wherein the EG is characterized by having a number of internal states <n and being capable of generating periodic enabling/disabling output signals such that the disable signals are optimally distributed among the enable signals.

Abstract: A method and a generator are described for high speed generation of an S-bit long pattern of a PRBS sequence to be periodically burst on to a bus of width S. The technique provides the calculation time being independent from the width S of the bus, and comprises calculation of all S bits of the PRBS pattern separately and in parallel by using previous PRBS patterns stored in a memory. For each bit to be generated, the generator performs a constant number N of logical operations required (by a polynomial defining the PRBS sequence.