Abstract: This invention teaches circuitry and methods for performing delay tests, including skewed-load, broad-side, and STUMPS-related tests. More particularly a logic circuit (10), such as an integrated circuit, includes at least one block of combinational logic (12) having a plurality of input nodes and at least one output node. The logic circuit further includes delay test circuitry (14, 16, 18) that is coupled to the plurality of input nodes and to the at least one output node. The delay test circuitry has a scan-chain register (14) having a plurality of outputs coupled to the plurality of input nodes for establishing at least first and second multi-bit test vectors at the plurality of input nodes. The delay test circuitry further includes a plurality of XOR gates that are coupled to the scan-chain register. The plurality of XOR gates have outputs for establishing logic states of bits of the second test vector at the plurality of input nodes.

Abstract: This invention addresses the testing and diagnosis of failures in the post-logic of products having embedded arrays. The post-logic is the combinational logic that is fed by the embedded array. Since there is no direct access to the post-logic (no direct controllability) it requires special handling. The testing method comprises initializing the array to random values; choosing an address from the array; reading out the information from that address, while applying random signals at the primary inputs. This process is continued for a predetermined number of cycles, while holding that address and applying different random signals at the primary inputs. The process is then repeated while choosing different addresses from the array. Fault diagnosis is accomplished by means of a notebook that retains the past history of the addresses chosen from the array.

Abstract: A cascaded arrangement of alternating AND gates and Exclusive-OR gates is employed in conjunction with an output from a pseudo-random signal generator to produce a weighted random pattern binary sequence which is granularly controllable in terms of user selected probabilities and for which the granularity level is readily controlled through the selection of a desirable number of cascaded stages.

Abstract: By selectively associating output signal lines with logic circuit input signal lines, it is possible to produce a combination logic circuit and latch string in which no pair of adjacent latches is connected to the same cone of logic in the logic circuit. This provides greatly improved capabilities for delay or AC circuit test with respect to the independence of test pairs of excitation data. The objective may also be achieved in whole or in part through the use of dummy latch elements which do not feed any logic circuit input signal lines.