Abstract: The present invention relates to methods, devices and systems for associating consumable data with an assay consumable used in a biological assay. Provided are assay systems and associated consumables, wherein the assay system adjusts one or more steps of an assay protocol based on consumable data specific for that consumable. Various types of consumable data are described, as well as methods of using such data in the conduct of an assay by an assay system. The present invention also relates to consumables (e.g., kits and reagent containers), software, data deployable bundles, computer-readable media, loading carts, instruments, systems, and methods, for performing automated biological assays.

Abstract: A vehicle computer system comprises one or more transceivers in communication with a radar-detector and an off-board server. The vehicle computer system further comprises a processor in the vehicle computer system in communication with the one or more transceivers. The processor is configured to receive a message from the radar-detector that includes information related to an alert, send data to the off-board server utilizing the one or more transceivers, the data including information related to the alert, and output at the VCS a notification based upon the message received from the radar-detector.

Abstract: A vehicle computer system comprises one or more transceivers in communication with a radar-detector and an off-board server. The vehicle computer system further comprises a processor in the vehicle computer system in communication with the one or more transceivers. The processor is configured to receive a message from the radar-detector that includes information related to an alert, send data to the off-board server utilizing the one or more transceivers, the data including information related to the alert, and output at the VCS a notification based upon the message received from the radar-detector.

Abstract: A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.

Abstract: A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.

Abstract: A combined computer media player and computer controller is disclosed. The apparatus includes a main housing with media controls thereon and a processor therein. An input port for connecting a mass storage device to the processor so the processor has access to media files thereon. An optical disc reader located in the housing and connected to the processor so the processor has access to media files thereon. The media files are playable, controllable, mixable and modifiable by the media controls. The apparatus further includes media output ports on the main housing that are connected to the processor to output a media files for listening or viewing. An input port for connecting the apparatus to a computer is included so the apparatus can control software running thereon.

Abstract: A media player for disc jockeys is disclosed. The media player includes a housing including a front face, a rear face, a left side and a right side. A plurality of input ports configured to connect a digital storage device containing a number of media tracks. A first and a second media output are included. The media player includes a first deck having a first media control interface configured to cue and play media tracks, and a second deck having a second media control interface configured to cue and play media tracks, and a global control interface including a main display screen divide into three portions. A digital mixing controller for accessing and controlling the digital storage device through the respective one of the respective input ports is also included.

Abstract: A media player for a disc jockey is disclosed. The media player includes a housing with a top surface with a surface defining a seat configured to received a portable media device with a library of media tracks stored thereon. The seat includes an input port for connecting to the portable media device. The media player includes a master output, a first and a second deck having a first and second media control interface configured to cue and play media tracks on a first and second channel, respectively, and a global control interface including a main display, a rotatable and pressable select knob and a number of multifunction controls having contextual function labels associated therewith for navigating menus and selecting menu choices contained therein.

Abstract: A floating point unit of an in-order-processor having a register array for storing a plurality of operands, a pipeline for executing floating point instructions with a plurality of stages, each stage having a stage register, data input registers (1A, 1B, 1C) for keeping operands to be processed. The data input registers form the first stage register of the pipeline. An input port loads operands from outside said floating point unit into one of said data input registers. A plurality of bypass-registers are provided, the input of which is connected to the input port, and the output of which is provided to the data input registers (1A, 1B, 1C), such that data propagating through the pipeline to be loaded into the register array can be immediately supplied to one or more particular data input registers (1A, 1B, 1C) from a respective bypass-register without a delay caused by additional pipeline stages to be propagated through.

Abstract: The present invention provides a circuit for increasing the noise tolerance of a receiving gate. This is accomplished by separating the circuit which sets the positive going threshold, from the circuit which sets the negative going threshold. This eliminates the need of making a design compromise equally suitable to both these threshold requirements. It is achieved by separating the logical drive for switching from a low to a high from the logical drive for switching from a high to a low. Alternate embodiments are presented. In one embodiment, separate drivers for PFET and NFET inverter inputs are employed together with an output latch circuit which prevents the output from being in a floating state. In an alternate embodiment the latch is included in-line with the gate output. An implementation of the invention in a two input AND gate is also described.

Abstract: A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing.

Abstract: A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing.

Abstract: A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing.

Abstract: Apparatus for joining a pair of flanged beams in an end-to-end relationship includes a pair of end plates each welded to an end of a corresponding one of the flanged beams. Each of the end plates has a notch therein which is aligned with the notch in the other plate and the end plates juxtapose. A clamp having a body portion which mates with the notches in the end plates, and having a radial flange on each side of the body portion, is secured with the body portion in the notches. The radial flanges of the clamp presses against the end plates to lock the plates securely together.