Abstract: An analog-to-digital converter including a voltage generation unit and a plurality of sub ADCs, each including a selection unit for selecting a voltage generated by the voltage generation unit based on a number and forwarding the selected voltage to a comparator arrangement. The selection unit includes first and second switch layers. The first switch layer includes a plurality of switch groups, each including a plurality of switch devices, each connected to a unique output terminal of the voltage generation unit with a first terminal and to a common node of the switch group with a second terminal. The second switch layer includes a switch device between the common node of each switch group and the first output terminal of the selection unit and a switch device between the common node and the second output terminal of the selection unit. A control unit generates control signals for the switch devices.

Abstract: A parallel successive-approximation analog-to-digital converter (PSA-ADC, 10) comprises a reference-voltage generation unit and a plurality of sub ADCs, (ADC-1, . . . , ADC-M) arranged for successive-approximation operation in a time-interleaved manner. Each sub ADC (ADC-1, . . . , ADC-M) comprises a reference-voltage selection unit (45, 45?) for selecting a reference voltage generated by the reference-voltage generation unit (35, 35?) based on a digital number XSA stored in a successive-approximation register (SAR, 70) of the sub ADC (ADC-1, . . . , ADC-M) and forwarding the selected reference voltage to a comparator arrangement of the sub ADC (ADC-1, . . . , ADC-M). The reference-voltage selection unit (45, 45?) comprises a ADC-1 first and a second switch layer. The first switch layer comprises a plurality of switch groups, wherein each switch group comprises a plurality of switch devices (120-0, . . . , 120-15), each operatively connected to a unique output terminals (40-0, . . .

Abstract: An analog-to-digital converter (1). The analog to digital converter (1) comprises a first range-control unit (100) adapted to generate a first range-control value for controlling a size of an input range of the analog-to-digital converter (1). The analog to digital converter further comprises a second range-control unit (200) adapted to generate a second range-control value for controlling a midpoint of the input range. Further, the analog-to-digital converter (1) comprises a reference-level unit (300) operatively connected to the first range-control unit (100) and the second range-control unit (200). The reference-level unit (300) is arranged to generate a plurality of reference levels at least based on the first and the second range-control value. The analog-to-digital converter further comprises a comparison unit (400) operatively connected to the second range-control unit (200) and the reference-level unit (300).

Abstract: A clock signal generator for generating clock signals to an integrated circuit. The clock signal generator comprises a delay-locked loop adapted to generate a plurality of mutually delayed clock phases based on a reference clock signal. The delay-locked loop is further adapted to select one of the plurality of clock phases as an output signal of the delay-locked loop in response to a first control signal, wherein said output signal is a first clock signal. The clock signal generator further comprises an inverter arranged to generate an inverse of the output signal and a multiplexer unit arranged to, in response to a clock-invert signal, forward either the output signal or the inverse of the output signal as a second clock signal.

Abstract: An analog-to-digital converter (1). The analog to digital converter (1) comprises a first range-control unit (100) adapted to generate a first range-control value for controlling a size of an input range of the analog-to-digital converter (1). The analog to digital converter further comprises a second range-control unit (200) adapted to generate a second range-control value for controlling a midpoint of the input range. Further, the analog-to-digital converter (1) comprises a reference-level unit (300) operatively connected to the first range-control unit (100) and the second range-control unit (200). The reference-level unit (300) is arranged to generate a plurality of reference levels at least based on the first and the second range-control value. The analog-to-digital converter further comprises a comparison unit (400) operatively connected to the second range-control unit (200) and the reference-level unit (300).

Abstract: A clock signal generator for generating clock signals to an integrated circuit. The clock signal generator comprises a delay-locked loop adapted to generate a plurality of mutually delayed clock phases based on a reference clock signal. The delay-locked loop is further adapted to select one of the plurality of clock phases as an output signal of the delay-locked loop in response to a first control signal, wherein said output signal is a first clock signal. The clock signal generator further comprises an inverter arranged to generate an inverse of the output signal and a multiplexer unit arranged to, in response to a clock-invert signal, forward either the output signal or the inverse of the output signal as a second clock signal.

Abstract: The values X(n) input to a current-steering digital-to-analog converter (49) are modified (41) before the actual conversion to compensate for conversion errors of the digital-to-analog converter. The input values are modified according to a model (43) of the digital-to-analog converter in which each output value of the digital-to-analog converter Y(n) is a sum of a desired value directly proportional to the respective input value and an error. The error is a product of the settled output value, i.e. the difference between the desired value and the previous output value Y(n?1) actually provided by the digital-to-analog converter, and a relative step error that is a function only of the respective input signal and is stored in a table. The relative step error can be a function also of the previous output signal and of the previous input signal. This model has a low complexity and is suitable for on-chip implementation.

Abstract: The values X(n) input to a current-steering digital-to-analog converter (49) are modified (41) before the actual conversion to compensate for conversion errors of the digital-to-analog converter. The input values are modified according to a model (43) of the digital-to-analog converter in which each output value of the digital-to-analog converter Y(n) is a sum of a desired value directly proportional to the respective input value and an error. The error is a product of the settled output value, i.e. the difference between the desired value and the previous output value Y(n?1) actually provided by the digital-to-analog converter, and a relative step error that is a function only of the respective input signal and is stored in a table. The relative step error can be a function also of the previous output signal and of the previous input signal. This model has a low complexity and is suitable for on-chip implementation.

Abstract: A D/A converter includes a triangular unit weight array. A decoder transforms digital samples into control signals having a linearly weighted binary representation. These control signal are used for activation/deactivation of entire rows or columns of the triangular unit weight array. Finally, the unit weights are combined into an analog output signal.

Abstract: To minimize the number of positions to be altered in a transition from one output data word to the next in a scrambler for scrambling successive, thermometer coded binary input data words comprising N bits into corresponding successive output data words also comprising N bits, the scrambler is adapted, if the number of bits of one binary value has increased from one input data word to the next, to maintain bits of said one binary value in positions in the corresponding output data word where the previous output data word had bits of said one binary value, and to randomize the remaining bits of said one binary value to positions in the corresponding output data word where the previous output data word had bits of the other binary value.

Abstract: A fully differential line driver, especially for twisted copper pairs. It includes two current amplifiers made in standard CMOS technique, each having an input and an output, the latter being connected via terminal resistors to a voltage source, which may be set to a larger voltage than that used for driving the CMOS amplifiers. Accordingly, a low output impedance can be combined with a large swing. Further, feedback is not necessary, avoiding problems like potential instability. A very low-impedance input makes it appropriate for connecting to a DAC, thus reducing distortion of its output signal. The driver is suitable for very-high-speed-digital-subscriber-line modems.

Abstract: To minimize the number of positions to be altered in a transition from one output data word to the next in a scrambler for scrambling successive, thermometer coded binary input data words comprising N bits into corresponding successive output data words also comprising N bits, the scrambler is adapted, if the number of bits of one binary value has increased from one input data word to the next, to maintain bits of said one binary value in positions in the corresponding output data word where the previous output data word had bits of said one binary value, and to randomize the remaining bits of said one binary value to positions in the corresponding output data word where the previous output data word had bits of the other binary value.