Patents by Inventor Jacob Zelnik

Jacob Zelnik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9213798
    Abstract: A method 100, a computer program product and a system of checking an integrated circuit layout for instances of a reference pattern is provided The method 100 comprises the steps of: i) receiving 102 the integrated circuit layout, ii) receiving 104 a drawing of the reference pattern from a user, iii) deducting 106 a basic pattern definition from the drawn reference pattern, iv) determining 108 a set of topological relation based on the drawn reference pattern, v) forming 110 a complex pattern description which is a combination of the deducted basic pattern definition and the set of topological relations, vi) checking 112 the integrated circuit layout for patterns that match the complex pattern description to find instances of the reference pattern in the integrated circuit layout, and vii) storing 114 found instances of the reference pattern.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: December 15, 2015
    Assignee: SAGE DESIGN AUTOMATION LTD
    Inventors: Jozefus Godefridus Gerardus Pancratius Van Gisbergen, Daniel James Blakely, Rob Oomens, Jacob Zelnik
  • Publication number: 20150154340
    Abstract: A method 100, a computer program product and a system of checking an integrated circuit layout for instances of a reference pattern is provided The method 100 comprises the steps of: i) receiving 102 the integrated circuit layout, ii) receiving 104 a drawing of the reference pattern from a user, iii) deducting 106 a basic pattern definition from the drawn reference pattern, iv) determining 108 a set of topological relation based on the drawn reference pattern, v) forming 110 a complex pattern description which is a combination of the deducted basic pattern definition and the set of topological relations, vi) checking 112 the integrated circuit layout for patterns that match the complex pattern description to find instances of the reference pattern in the integrated circuit layout, and vii) storing 114 found instances of the reference pattern.
    Type: Application
    Filed: May 15, 2012
    Publication date: June 4, 2015
    Applicant: SAGANTEC ISRAEL LTD.
    Inventors: Jozefus G. G. P. Van Gisbergen, Daniel James Blakely, Rob Oomens, Jacob Zelnik