Patents by Inventor Jacobus Verbree

Jacobus Verbree has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Test access architecture for TSV-based 3D stacked ICS
    Patent number: 9239359
    Abstract: A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: January 19, 2016
    Assignees: IMEC, Stichting IMEC Nederland
    Inventors: Erik Jan Marinissen, Jacobus Verbree, Mario Konijnenburg, Chun-Chuan Chi