Abstract: A method for on demand functional verification of a software model of an application specific integrated circuit (ASIC), in a low-level programming language, which separately handles the creation of the model and the debugging of the functional verification tests to be applied to the model in order to create a verification platform. In a transmission mode, an autonomous circuit emulator is created by replacing the model in a low level programming language physically describing the circuit to be validated with a high level description generating response data in accordance with the functional specification of the design as a function of stimuli received. A verification mode includes integration of the software model in low level language of the circuit resulting from the design into a verification platform, and creation of a connection of a previously validated autonomous circuit emulator to the interfaces of the software model.

Abstract: The present invention relates to a method for on demand functional verification of a software model of an application specific integrated circuit (ASIC), in a low-level programming language (for example of the HDL type), which separately handles the creation of the model and the debugging of the functional verification tests to be applied to the model of the circuit in order to create a verification platform. The method for verification comprises a transmission mode and a verification mode. In the transmission mode an autonomous circuit emulator (1), is created or obtained by replacing the model in a low level programming language physically describing the circuit under design to be validated with a high level (for example C++) abstract description generating response data structures in accordance with the functional specification (20) of the design as a function of the stimuli received.

Abstract: The present invention concerns a method for the functional verification of a software model (40) of an integrated circuit on demand (ASIC), in a low-level language (for example of the HDL type), which separately handles the creation of the model and the debugging of the functional verification tests to be applied to the model of the circuit in order to create a verification platform, comprising the following two steps:

Abstract: A Process for coherent management of exchanges between memories in an information system having at least two levels of memories. The information system in one embodiment is constituted by a central subsystem which can communicate with one or more peripheral subsystems by means of input-output units. The central subsystem includes several processors linked to a central memory and to the input-output units. Each processor includes an associated cache memory linked with the central memory. In operation, each processor executes the instructions of programs contained in an associated cache memory. If the cache memory does not contain the data necessary to the associated processor, the data is read in the central memory and a copy is made using memory blocks of predetermined size. The coherent management of exchange between memories is achieved by dynamically applying a management mode selected as a function of the use that is made of each block.