Abstract: An electromagnetic shield device for printed circuit boards (PCBs) which, in one embodiment, is made of conductive material and comprised of two parts. In another embodiment, the device is a singular element. In both examples, press-fit or compliant pins may be used to electrically couple the device to the PCB's ground layer. Alternatively, projecting pins or flat conductive plates can be used to provide this coupling. The device is also adjustable to accommodate PCBs of varying thicknesses. The device provides for added PCB stiffness while assuring prevention of electromagnetic radiation from the PCB's edge.

Abstract: An electromagnetic shield device for printed circuit boards (PCBs) which, in one embodiment, is made of conductive material and comprised of two parts. In another embodiment, the device is a singular element. In both examples, press-fit or compliant pins may be used to electrically couple the device to the PCB's ground layer. Alternatively, projecting pins or flat conductive plates can be used to provide this coupling. The device is also adjustable to accommodate PCBs of varying thicknesses. The device provides for added PCB stiffness while assuring prevention of electromagnetic radiation from the PCB's edge.

Abstract: A method and apparatus for distribution of electrical signals in a circuit board. Specifically, the circuit board comprises a printed circuit board and a plurality of connectors attached to the circuit board for receiving components such as logic cards which each require a clock input. Each of the connectors may have a plurality of pins. A plurality of electrical conductors associated with the circuit board electrically couple a corresponding pin for a clock input from each connector to a common point by individual one of the plurality of electrical conductors. Each of the plurality of electrical conductors are so arranged that to have approximately the same length.

Abstract: A distribution mechanism includes a scheduling device which partitions a common timing signal with a period T into n slots of t duration each, a configuration table having n addressable locations with each of the n locations storing communication control information and addressable by slot numbers generated by the scheduling device and a distribution buffer device (2) having at least a first and a second part, with each part having n addressable locations addressed by control information provided by the configuration table during each slot period to cause an interface involved in the to be established communications during a selected slot period, to write the information to be transmitted in one part of the distribution buffer and the information to be received by the interface to be read from the other part of the distribution buffer at addresses derived from the communication control information and the slot generated by the schedule means.

Abstract: The bit streams, transporting the frames, received from lines (6) are placed in register 12 in such a way that n bits are processed in parallel during a time interval T. Parallel processor 10 counts the consecutive logical "1" bits beginning at the low order (left most) bit of the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result, it reassembles N-bit characters, with N<n, in register (16). The frame characters to be sent on lines (6) are stored into register (28), and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive logical "1's" as a function of the value of the N bit and as a function of the bits of the previous character, to store into register (32), the bits which are sent on lines (6).