Abstract: System for generating a pulsed signal of the ultra wideband type, comprising a device for direct digital frequency synthesis (DDS) comprising a phase accumulator (ACCP) able to deliver at a first frequency (Fclk) phases coded on i bits and spaced apart by a phase increment (?p) differing by a power of two and situated in the vicinity of 2i-1, processing means (MT) able to receive said phases and arranged so as to deliver an amplitude-modulated output signal (SG) whose envelope exhibits a succession of regions respectively delimited by zones of zero amplitude (ZA, ZB), each amplitude-modulated signal part situated in one of said regions forming a pulse of the ultra wideband type (IMP) whose central frequency is equal to said first frequency and whose width depends on the value of the phase increment, and control means (MC) able to regulate the operation of the digital synthesis device so as to selectively deliver one or more pulses of the ultra wideband type.

Abstract: System for generating a pulsed signal of the ultra wideband type, comprising a device for direct digital frequency synthesis (DDS) comprising a phase accumulator (ACCP) able to deliver at a first frequency (Fclk) phases coded on i bits and spaced apart by a phase increment (?p) differing by a power of two and situated in the vicinity of 2i?1, processing means (MT) able to receive said phases and arranged so as to deliver an amplitude-modulated output signal (SG) whose envelope exhibits a succession of regions respectively delimited by zones of zero amplitude (ZA, ZB), each amplitude-modulated signal part situated in one of said regions forming a pulse of the ultra wideband type (IMP) whose central frequency is equal to said first frequency and whose width depends on the value of the phase increment, and control means (MC) able to regulate the operation of the digital synthesis device so as to selectively deliver one or more pulses of the ultra wideband type.

Abstract: A limiter circuit having a field effect transistor whose bias circuit is constituted by two constant voltage feeds: one for its gate and the other for its drain, with a resistive load being connected in series with the feed to the gate of the transistor. The invention is particularly applicable to space telecommunications.