Patents by Inventor Jacques J. Bertrand
Jacques J. Bertrand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7023059Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain regions and on the gate. Trenches are formed in the semiconductor substrate around the gate. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.Type: GrantFiled: March 1, 2004Date of Patent: April 4, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Darin A. Chan, Simon Siu-Sing Chan, Jeffrey P. Patton, Jacques J. Bertrand
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Patent number: 6841449Abstract: Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are formed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with oxygen gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.Type: GrantFiled: February 4, 2002Date of Patent: January 11, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Jacques J. Bertrand, George J. Kluth
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Patent number: 6730587Abstract: Nickel silicidation of a gate electrode is controlled using a titanium barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of titanium thereon and an upper polycrystalline silicon layer on the titanium layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel silicide and a titanium silicide barrier layer is formed preventing nickel from reacting with the lower polycrystalline silicon layer.Type: GrantFiled: December 7, 2000Date of Patent: May 4, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Jacques J. Bertrand, Christy Mei-Chu Woo, Minh Van Ngo, George Kluth
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Patent number: 6632740Abstract: Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are fomxed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with nitrogen gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.Type: GrantFiled: February 4, 2002Date of Patent: October 14, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Jacques J. Bertrand, George J. Kluth
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Patent number: 6627504Abstract: Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by recessing the silicon nitride spacers and forming barrier spacers on top of the silicon nitride spacers. The barrier spacers prevent silicon migration and hence the formation of bridging silicide on the silicon nitride sidewall spacers.Type: GrantFiled: February 7, 2001Date of Patent: September 30, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Jacques J. Bertrand, George J. Kluth
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Patent number: 6605513Abstract: A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.Type: GrantFiled: December 6, 2000Date of Patent: August 12, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Eric N. Paton, Ercan Adem, Jacques J. Bertrand, Paul R. Besser, Matthew S. Buynoski, John Clayton Foster, Paul L. King, George Jonathan Kluth, Minh Van Ngo, Christy Mei-Chu Woo
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Patent number: 6562718Abstract: A method of forming a fully silicidized gate of a semiconductor device includes forming silicide in active regions and a portion of a gate. A shield layer is blanket deposited over the device. The top surface of the gate electrode is then exposed. A refractory metal layer is deposited and annealing is performed to cause the metal to react with the gate and fully silicidize the gate, with the shield layer protecting the active regions of the device from further silicidization to thereby prevent spiking and current leakage in the active regions.Type: GrantFiled: December 6, 2000Date of Patent: May 13, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Qi Xiang, Ercan Adem, Jacques J. Bertrand, Paul R. Besser, Matthew S. Buynoski, John C. Foster, Paul L. King, George J. Kluth, Minh V. Ngo, Eric N. Paton, Christy Mei-Chu Woo
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Patent number: 6541866Abstract: Nickel silicidation of a gate electrode is controlled using a cobalt barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of cobalt thereon and an upper polycrystalline silicon layer on the cobalt layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel suicide and a cobalt silicide barrier layer is formed preventing nickel from reacting with the lower polycrystalline silicon layer.Type: GrantFiled: February 7, 2001Date of Patent: April 1, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Jacques J. Bertrand, Christy Mei-Chu Woo, Minh Van Ngo, George J. Kluth
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Patent number: 6507123Abstract: A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide. first and second sets of sidewall spacers and nickel suicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first set of sidewall spacers are formed undoped silicon oxide and are respectively disposed adjacent the first and second sidewalls. The second set of sidewall spacers are formed from silicon nitride and are respectively disposed adjacent the first set of sidewall spacers. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. The second set of sidewall spacers being formed from undoped silicon oxide prevents the formation of nickel silicide on the second set of sidewall spacers. A method of manufacturing the semiconductor device is also disclosed.Type: GrantFiled: October 5, 2000Date of Patent: January 14, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Christy Mei-Chu Woo, Minh Van Ngo, Jacques J. Bertrand
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Patent number: 6432817Abstract: Nickel silicidation of a gate electrode is controlled using a tungsten silicide barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of tungsten silicide thereon and an upper polycrystalline silicon layer on the tungsten silicide layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel silicide and the tungsten silicide barrier layer prevents nickel from reacting with the lower polycrystalline silicon layer.Type: GrantFiled: December 7, 2000Date of Patent: August 13, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Jacques J. Bertrand, Christy Mei-Chu Woo, Minh Van Ngo, George Kluth
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Publication number: 20020068408Abstract: A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.Type: ApplicationFiled: December 6, 2000Publication date: June 6, 2002Applicant: Advanced Micro Devices, Inc.Inventors: Eric N. Paton, Ercan Adem, Jacques J. Bertrand, Paul R. Besser, Matthew S. Buynoski, John Clayton Foster, Paul L. King, George Jonathan Kluth, Minh Van Ngo, Christy Mei-Chu Woo