Patents by Inventor Jacques Majos

Jacques Majos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040222862
    Abstract: A voltage-controlled oscillator includes an oscillating stage with two coupled CMOS inverters forming a quadrupole with two inputs and with two outputs, and two oscillating circuits placed respectively between the inputs and the outputs of the inverters and each having an inductor, the quadrupole being designed so that the outputs of the quadrupole are in phase. The inductors of the oscillating circuits are produced in MOS technology and are superposed one on top of the other.
    Type: Application
    Filed: March 22, 2004
    Publication date: November 11, 2004
    Inventor: Jacques Majos
  • Patent number: 6701445
    Abstract: A frequency control system includes a voltage-controlled oscillator, a sampling circuit for sampling a clock signal produced by the oscillator for two consecutive transitions of an unstable incoming digital signal, and a frequency comparator for incrementing and decrementing a transition upcounter-downcounter controlling the oscillator. The system tolerates variation of the frequency of the incoming signal about a mean value, which has no effect on a clock signal to be extracted by means of a phase comparator or on the synthesized clock signal supplied by the oscillator if the incoming signal contains a high level of jitter and is supplied by a programmable frequency divider.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: March 2, 2004
    Assignee: France Telecom
    Inventor: Jacques Majos
  • Patent number: 5640366
    Abstract: The sequential-access asynchronous memory device comprises an asynchronous double-port random access memory (MVDP), a write address generator (CE) for delivering to the input port of the memory, in response to write enable signals (ATE), successive write address information (ADE) respectively associated with successive data (DE) to be stored sequentially in a predetermined order of writing, a read address generator (CL) for delivering to the output port of the memory, in response to read enable signals (ATL), successive read address information (ADL) respectively associated with successive data (DL) to be read sequentially in a predetermined order of reading, a device for detecting the stability of the address information delivered by the address generators, and a device (GAE, GAL, ST1, ST2) for determining the level of fill of the memory from the stable address information delivered by the address generators.
    Type: Grant
    Filed: September 12, 1995
    Date of Patent: June 17, 1997
    Assignee: France Telecom
    Inventors: Jacques Majos, Daniel Weil
  • Patent number: 5319369
    Abstract: Typically, a parallel-to-serial converter comprises a parallel-to-parallel register and a parallel-to-serial register. According to the prior art, a first clock signal the transfer of incoming parallel data words to outputs of the parallel-to-parallel register whereas the loading of the parallel-to-parallel register is rhythmed by a second clock signal which is independent of the first clock signal. According to the invention, a local base time produces the second loading clock signal and two clock signals substantially in phase-opposition so that there is time dependence between these signals. A phase analyzing circuit derives a control signal for selecting one of the two clock signals which are in phase-opposition as a function of a phase shift between the incoming parallel data words and the first clock signal.
    Type: Grant
    Filed: July 19, 1993
    Date of Patent: June 7, 1994
    Assignee: France Telecom
    Inventors: Jacques Majos, Alain Chemarin
  • Patent number: 5319361
    Abstract: A circuit managing numbers of accesses to logic resources, such as buffer memory data cells in a time switching system. The circuit is structured around a counting cell matrix including a synchronous counter storing an instananeous number of accesses relating to a corresponding data cell of the buffer memory. This encoded access number is representative of the number of outgoing multiplex ways from the system to which a data block received on an incoming multiplex way in the system must still be diffused. A given circuit operating cycle includes the loading of a counter by an access number corresponding to a free data cell address supplied by matrix column and row encoders during a cycle preceding the given cycle. This loading is obtained by selecting a column and row by cell-to-be-charged column and row decoders, and by applying the encoded access number to an input bus of the counters in the cells.
    Type: Grant
    Filed: March 27, 1992
    Date of Patent: June 7, 1994
    Assignee: France Telecom
    Inventors: Jacques Majos, Alain Andre, Henri Teyssier
  • Patent number: 4219828
    Abstract: A metal-oxide-semiconductor field-effect device for constituting a single logic inverter stage. It includes a multidrain transistor operating in enhancement mode and a load transistor, both of monochannel metal-oxide-semiconductor structure. The inverter transistor comprises a single gate region and several drain regions. The single gate region and the single channel region of the inverter multidrain transistor are superimposed on both implantation planes separated by a thin insulating layer, entirely surround each drain region of the inverter multidrain transistor and are entirely surrounded by the single source region of the inverter multidrain transistor.
    Type: Grant
    Filed: December 4, 1978
    Date of Patent: August 26, 1980
    Inventors: Jean-Louis Lardy, Jacques Majos
  • Patent number: 4027147
    Abstract: Binary multiplication unit for multiplying a plurality of successively entering multiplicands by a common multiplier. The unit admits a high rate incoming and outgoing flow of data, but the time for implementing a multiplication is relatively long and substantially greater than the time separating two successively entering multiplicands. The unit comprises means for receiving a multiplier word and successive multiplicand words and for partitioning the multiplicands into multiplicand subwords. To the multiplicand subwords there corresponds shifted mutliplicand subwords which are deprived of their lowest weight bit and completed by a highest weight bit which is the lowest weight of the adjacent multiplicand subword. The shifted subwords are multiplied by the first bit of the multiplier word and the subwords are multiplied by the second bit of the multiplier word, and the partial products obtained are added to form first "subsum" words.
    Type: Grant
    Filed: February 18, 1976
    Date of Patent: May 31, 1977
    Inventors: Jacques Majos, Jean-Louis A. Lardy
  • Patent number: 4017693
    Abstract: The invention relates to a synthesizer of multifrequency code signals for a keyboard type telephone station, more particularly to a generator producing dialing signals or more generally recorder signals embodied by frequencies associated 2 by 2 in a 2-amongst-N code to represent decimal-notation digits and, if necessary, other signal-service signals. A dialing code of such a kind can be e.g. the SOCOTEL multifrequency code recommended by the CCITT.
    Type: Grant
    Filed: September 29, 1975
    Date of Patent: April 12, 1977
    Inventors: Bernard G. Roche, Jacques Majos, Jean-Louis A. Lardy
  • Patent number: RE41031
    Abstract: A frequency control system includes a voltage-controlled oscillator, a sampling circuit for sampling a clock signal produced by the oscillator for two consecutive transitions of an unstable incoming digital signal, and a frequency comparator for incrementing and decrementing a transition upcounter-downcounter controlling the oscillator. The system tolerates variation of the frequency of the incoming signal about a mean value, which has no effect on a clock signal to be extracted by means of a phase comparator or on the synthesized clock signal supplied by the oscillator if the incoming signal contains a high level of jitter and is supplied by a programmable frequency divider.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: December 1, 2009
    Inventor: Jacques Majos