Abstract: A method for detecting a locked condition of a demodulator of at least one signal that may have discrete levels defining a constellation of nominal points in a plane. The method includes the steps of defining reference areas about the nominal points, a reference area being separated from another by a band or an angular sector crossing the origin of the constellation plane, and indicating a locked condition if the ratio of points occurring in the reference areas is above the probability for points to occur in the reference area, when the demodulator is wrongly adjusted.

Abstract: A Reed-Solomon decoder receives code sequences of M coefficients having a maximum value N, t of which can be corrected. The Reed-Solomon decoder includes 2t polynomial counters successively receiving the M coefficients of each code sequence, the polynomial counter of rank i (i=0,1 . . . 2t-1), providing the coefficient of the term of degree i of a syndrome polynomial. A circuit provides the coefficients of an error locator polynomial from the coefficients of the syndrome polynomial. Another circuit finds the roots of the error locator polynomial by successively trying values .alpha..sup.1 to .alpha..sup.M. The polynomial counter of rank i is preceded by a multiplier by .alpha..sup.(B+i)(N-M), .alpha..sup.B+i being the i-th root of the code generator polynomial.

Abstract: A convolution decoder includes, for each state S of a shift register receiving an initial signal, an add-compare-select circuit which provides a one-bit decision for selecting either one of states 2S or 2S+1 as a state preceding the current state S. A decoding element traces back the memory according to a path indicated by the decisions stored in the memory in order to restore the succession of states of the initial signal. Each calculation cell associated with a state S further includes means for establishing a complex R-bit decision comprising, by decreasing weight, the one-bit decision of the calculation cell and the R-1 most significant bits of the complex decision established by the cell associated with the selected state 2S or 2S+1.

Abstract: In a Reed-Solomon error correction system, the coefficients of the syndrome polynomial of degree 2t-1 are stored in a first set of registers R, coefficients 0,0 . . . ,0,1,0 are stored in a second set of registers .lambda., and a first number is stored in a counter. Coefficients 1,0 . . . ,0 are stored in a third set of registers Q, zeroes are stored in a fourth set of registers .mu., and a number exceeding the first number by 1 is stored in an indicator register.a) If the content of the counter is higher than or equal to the content of the indicator register, or if the content of the last register of the first set of registers R is zero, value Q.sub.2t-1 R.sub.i-1 +R.sub.2t-1 Q.sub.i-1 is stored in each register R.sub.i of the first set of registers R, and value Q.sub.2t-1 .lambda..sub.i-1 +R.sub.2t-1 .lambda..sub.i-1 is stored in each register .lambda..sub.i of the third set of registers .lambda..b) Otherwise, the contents of the first set of registers R, the second set of registers .lambda.

Abstract: A method for detecting a locked condition of a demodulator of at least one signal that may have discrete levels defining a constellation of nominal points in a plane. The method includes the steps of defining reference areas about the nominal points, a reference area being separated from another by a band or an angular sector crossing the origin of the constellation plane, and indicating a locked condition if the ratio of points occurring in the reference areas is above the probability for points to occur in the reference areas when the demodulator is wrongly adjusted.

Abstract: A filter uses a digital integrator that establishes the sum, weighted by a coefficient B, of q1-bit input data arriving at a frequency F. The integrator includes a first p-bit shift-right register; a second q-bit shift-right register, circularly connected and storing the current input data in its most significant bits; and a full bit adder having two inputs respectively connected to the outputs of the first and second shift registers, and an output connected to the input of the first shift register. A sequencer enables the shifting of the first register during p clock cycles, and the shifting of the second register during q clock cycles starting b cycles after the beginning of the p cycles, number b being selected as a function of coefficient B.

Abstract: A circuit for inverting a number of n bits of a finite field of 2.sup.n =N+1 elements comprises a first circuit for raising to the power t=2.sup.n/2 receiving the number to invert. A first complete multiplier receives the number to invert and the output of the circuit for raising to the power t. A second circuit provides the product of the output of the circuit for raising to the power t and the inverse of the output of the first complete multiplier.

Abstract: A digital phase comparator supplies digital values corresponding to the phase shifts between a first signal having a duty cycle of approximately 0.5 and a second signal. The comparator includes a one-way counter initialized at the frequency of the first signal and clocked by a clock signal having a high frequency with respect to the frequency of the first and second signals. A logic gate enables the counter when the first and second signals are in respective predetermined states. A phase shift is considered to be zero when it corresponds approximately to one half of the counter's capacity.

Abstract: A circuit that extracts the synchronization signal from a composite video signal. The circuit includes a stage for aligning the low level of the synchronization signal interval with a reference voltage; a stage for detecting the signal suppression level and a comparator for comparing the aligned video signal with a value intermediate between the low level of the synchronization interval and the signal suppression level. The detecting stage includes a second comparator charging or discharging a capacitor depending on the polarity of the voltage difference across its inputs. The ratio Ic/Id between the values of the charging and discharging currents is selected (approximately equal to 8 in one embodiment) to obtain the suitable value Vsup at the second input of the comparator.

Abstract: A frequency synthesizer provides a synthesized signal. The synthesizer includes an oscillator that supplies a fast clock signal to a divider programmable by a digital data. The most significant bits of the digital data are provided to the programmable divider, and the least significant bits are provided to an accumulator that cooperates with the programmable divider to increment by one unit its division rank when the accumulator overflows. The synthesizer further includes a generator for generating n increasing delay phases of the synthesized signal; a comparator for comparing the content of the accumulator with n ranges of possible increasing values; and circuits for selecting, as the synthesized signal, the phase whose rank corresponds to the rank of the range within which the content of the accumulator is comprised.

Abstract: This device for converting a very-low-amplitude steady voltage signal into an alternating voltage signal, of the type comprising a centre-tapped transformer (1) associated with a transistor (3,4) chopper (2), is characterised in that the transformer (1) and the transistors (3,4) are arranged in a housing (15) held at very low temperature and in which is arranged a material (20) for thermal insulation of the transistors (3,4) with respect to the rest of the housing so as to reduce temperature fluctuations and allow operation of these transistors by self-heating due to their drive current.

Abstract: A device synchronizes an internal signal with respect to a reference signal, each signal comprising pulses normally occurring at a rated frequency. The device uses a phase comparator to analyze the phase of the internal signal and the reference signal and produce one logic state if the phase of the internal signal is in advance of the phase of the reference signal and a second logic state otherwise. A programmable frequency divider divides an internal clock signal by a first number if the phase comparator signal produces the first logic state or by a second number if the phase comparator produces the second logic state. A multiplexer provides the programmable divider with either the first number or the second number depending on the logic state produced the phase comparator. The device also includes a storage element for sequentially storing a predetermined number of the latest logic states of the phase comparator.

Abstract: This invention relates to compositions comprising 1-aryl-4,5-dihydro-1,2,4-triazol-5(1H)-ones (triazolinones) in combination with the herbicide (2,4-dichlorophenoxy)acetic acid (2,4-D), or like substituted phenoxyalkanoic acids, or esters, or alkali metal or ammonium salts thereof; or with certain herbicidal sulfonylureas, or mixtures of these classes of compounds, to provide herbicidal compositions which are highly effective against a broad array of crop weeds, particularly broadleaf weeds, in crops such as wheat.

Abstract: An extractor for digital data transmitted at a first determined frequency (f0) through a video channel after a burst of 0s and 1s emitted at a first frequency (f0). A comparator (1) compares the input signal with a threshold level. A threshold level is provided by an up/down counter (12) operating at a frequency (F0) multiple of the first frequency, the up/down counting input of which is connected to the output of the comparator (1), and a digital/analog converter (16) receiving the output of the up/down counter and supplying the threshold level (V.sub.T).

Abstract: A linear interpolation operator for determining the value y of a function of x when one knows the value y.sub.1 corresponding to x.sub.1, and a value y.sub.2 corresponding to x.sub.2 (where x.sub.2 >x.gtoreq.x.sub.1), comprises a first calculation circuit which determines the equation (x.sub.m +x.sub.M)/2; a second calculation which determines the equation (y.sub.m +y.sub.M)/2; a comparison circuit which compares x with (x.sub.m +x.sub.M)/2 so as to determine which one of the intervals [x.sub.m,(x.sub.m +x.sub.M)2], [(x.sub.m +x.sub.M)/2, x.sub.M ] contains x and to feed back the limits of the selected interval into the first calculation circuit and the limits of the interval corresponding in y into the second calculation circuit.

Abstract: The industrial installation comprises an active zone (III) with which there are associated means for measurement and for command and a control position (I) separated from the active zone. Means for measurement, for control and for command (15) located in the active zone are supplied with luminous radiations, from the control position, through an optical fibre (8) joining the active zone to the control position. Radiation having a broad spectral band is emitted in the fiber (8) from the control position (I) and then divided in order to obtain unitary radiations for supplying each of the means (15). The invention applies to nuclear reactors.

Abstract: Being given the number among P of a data, an attempt is made to find the number among N of said data in a group of N data incorporating P selected data. The sequence numbers of these P data appear in a register having N locations and the sequence number of the chosen data among P appears in a second register with P locations. The locations of the second register are connected to the rows of a switching circuit, each of these rows having N cells, which connect the input of one cell to the following cell of the same rank or to the following cell of the lower rank, as a function of the content of the corresponding location of the first register. Thus, at the outputs of the columns there are signals, whereof only one is at a level different from the others and corresponding to the number j among N of the chosen data.

Abstract: A method of selectively controlling weeds in crop areas, notably vineyards or fruit plantations, by applying a composition that includes different active herbicidal ingredients; the composition comprises a synergistic combination of about 1 part, by weight, of methyl-5-(2,4-dichlorophenoxy)-2-nitrobenzoate as a first active ingredient, and about 1 to 5 parts, by weight, of 3-tert.butyl-5-chloro-6-methyl-uracil as a second active ingredient.The novel composition comprises said synergistic combination and may further contain a mineral oil and adjuvants such as an emulsifier.