Patents by Inventor Jacques-Oliver Piednoir

Jacques-Oliver Piednoir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4967367
    Abstract: A system and method is disclosed for generating a synthetic netlist which mimics the size and complexity of a specified target circuit. The first step of synthetic netlist generation is to generate an abstract of the netlist of a known circuit of the same type as the specified target circuit. Information in the abstract specifies the relative usage rates of the circuit elements in the known circuit and the complexity of the interconnections between circuit elements and circuit signals. The second step is to generate a synthetic netlist, scaled to include a specified number of circuit elements. The circuit elements in the synthetic netlist are interconnected in a sequential process so as to have the interconnection complexity specified by the abstract of the known circuit.
    Type: Grant
    Filed: November 21, 1988
    Date of Patent: October 30, 1990
    Assignee: VLSI Technology, Inc.
    Inventor: Jacques-Oliver Piednoir