Abstract: The present invention relates to a signal synchronization circuit comprising at least one synchronizer (2.1-2.2) comprising a number N of series connected clock delay elements (3.1-3.3), N being equal to or greater than unity and a clock signal generator (1) arranged for generating a modulated clock signal adapted to clock the clock delay element (3.1-3.3) or elements of the at least one synchronizer (2.1-2.2). The clock generator (1) is arranged to receive a clock signal (5) and at least one operating value (6) and to generate the modulated clock signal (1 out) from the clock signal (5) modified based on the operating value (6).

Abstract: The present invention relates to a signal synchronization circuit comprising at least one synchronizer (2.1-2.2) comprising a number N of series connected clock delay elements (3.1-3.3), N being equal to or greater than unity and a clock signal generator (1) arranged for generating a modulated clock signal adapted to clock the clock delay element (3.1-3.3) or elements of the at least one synchronizer (2.1-2.2). The clock generator (1) is arranged to receive a clock signal (5) and at least one operating value (6) and to generate the modulated clock signal (1 out) from the clock signal (5) modified based on the operating value (6).

Abstract: A system for testing an integrated circuit, the integrated circuit including: flip-flops connected to a logic block and the test system including circuitry for connecting the flip-flops as a register, circuitry for inhibiting the different elements of the logic block capable of disturbing the sequencing of the register or the propagation of the signals into the logic block, and a control circuit for separately controlling the different inhibiting circuits and the circuitry for connecting the flip-flops as a register.

Abstract: A system for testing an integrated circuit, the integrated circuit including: flip-flops connected to a logic block and the test system including circuitry for connecting the flip-flops as a register, circuitry for inhibiting the different elements of the logic block capable of disturbing the sequencing of the register or the propagation of the signals into the logic block, and a control circuit for separately controlling the different inhibiting circuits and the circuitry for connecting the flip-flops as a register.

Abstract: In a device for descrambling scrambled digital data, the digital data are grouped into parallel combinations of bits before being descrambled. The combinations of bits are descrambled and then split back into a serial stream of bits.

Abstract: The present invention relates to an electronic device of the “SMARTCARD” type including a single input/output lead for communicating with the microcontroller from the outside. Interface registers between a peripheral and the microcontroller are likely to be connected according to a shift register configuration forming a test scan path accessible in series and clocked by a clock signal to be applied to a peripheral clock lead. A test aid circuit, in a scan mode, connects the interface registers according to the shift register configuration, the scan mode being selected when a test bit, accessible through the input/output lead, is enabled and the input/output lead is forced from the outside to a state distinct from its default state.

Abstract: The present invention relates to a method for generating pulses using a microprocessor including a CPU and a counter programmable by at least one control bit and of a counting threshold, consisting of generating a first edge of a pulse by unconditionally forcing the state of an output signal of the counter to a state corresponding to a state of the control bit, and generating a second edge of the pulse by switching the state of the output signal at the end of the counting threshold.

Abstract: The present invention relates to a method for generating pulse trains by means of a microprocessor, consisting of generating an envelope signal by means of a timer which is programmable by a CPU, the width of a square wave of the envelope signal corresponding to the width of the pulse trains, generating a carrier signal having a predetermined frequency, and modulating the envelope signal with the carrier.