Patents by Inventor Jacques Reberga

Jacques Reberga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7969131
    Abstract: The present invention relates to a converter circuit and a conversion method for converting an input signal of a first value to an output signal of a second value based on a switched operating mode, wherein an output feedback loop (40) and an additional input forward control loop (60) are provided. The additional input forward control loop (60) serves to correctly control a switching parameter not only with respect to the output load but also over a wide input voltage range. This leads to an improved power efficiency and reliability of the converter circuit.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: June 28, 2011
    Assignee: NXP B.V.
    Inventors: Jacques Reberga, Melaine Philip, Emeric Uguen
  • Publication number: 20080298089
    Abstract: The present invention relates to a converter circuit and a conversion method for converting an input signal of a first value to an output signal of a second value based on a switched operating mode, wherein an output feedback loop (40) and an additional input forward control loop (60) are provided. The additional input forward control loop (60) serves to correctly control a switching parameter not only with respect to the output load but also over a wide input voltage range. This leads to an improved power efficiency and reliability of the converter circuit.
    Type: Application
    Filed: August 2, 2005
    Publication date: December 4, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Jacques Reberga, Melaine Philip, Emeric Uguen
  • Publication number: 20080270654
    Abstract: A bus system (BS) for selectively controlling a plurality of identical slave circuits (slave A) comprises a bus (B) having a clock line (CLOCK) and at least one data line (DATA). The bus system (BS) includes at least one master circuit (1) and a plurality of slave circuits (2) with a group of identical slave circuits (slave A) connected to said bus (B). Each of the identical slave circuits (slave A) comprises an input-terminal (AD). The bus system (BS) further includes a selection circuit (3) connected to said bus (B), said selection circuit (3) is connected to each of said input-terminals (AD) for configuring at least one of the identical slave circuits (slave A) to be addressable by a master circuit (1) via said at least one data line (DATA).
    Type: Application
    Filed: April 20, 2005
    Publication date: October 30, 2008
    Applicant: Koninklijke Philips Electronics N.V.
    Inventor: Jacques Reberga
  • Publication number: 20080258699
    Abstract: The present invention relates to a converter circuit and a conversion method for converting an input signal to an output signal of a predetermined value based on a switched operating mode, wherein a first control loop (40) is provided for comparing the predetermined value of the output signal to a first reference value and for generating a feedback signal in response to the comparison result; and wherein a second control loop (60) is provided for comparing a time period passed until the feedback signal is generated to a second reference value and for controlling the switching parameter of the switched operating mode in response to the comparison result. As a result, the output signal is correctly controlled not only with respect to the output load but also over a wide range of the input signal, so that power efficiency and reliability can be optimized.
    Type: Application
    Filed: September 7, 2005
    Publication date: October 23, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Jacques Reberga, Melaine Philip
  • Publication number: 20040128603
    Abstract: A device for testing the conformity of an electronic connection (1), the device comprising a first signal generator (3) supplying a sequence of input bits to a first extremity (E) of the connection (1), and an error detection device (6) receiving a sequence of output bits from a second extremity (S) of the connection (1), in response to the sequence of input bits.
    Type: Application
    Filed: November 12, 2003
    Publication date: July 1, 2004
    Inventor: Jacques Reberga