Abstract: A motor vehicle axle system including two longitudinal arms made of molded material and a torsionally flexible cross bracing made of high strength material different from the material of the arms, each arm including a lug for assembling by structural bonding the cross bracing to the arms. Each lug has an assembling edge configured to be assembled to one end of the cross bracing by generating self-binding with a surface of the cross bracing, an adhesive layer being applied between the assembling edge and the surface of the cross bracing, and the assembling edge of each lug has a variable thickness along its periphery and in the direction of the lug axis, the thickness being selected so as to minimize stresses exerted on the adhesive in the assembling zone. A method assembles the motor vehicle axle system.

Abstract: A motor vehicle axle system including two longitudinal arms made of molded material and a torsionally flexible cross bracing made of high strength material different from the material of the arms, each arm including a lug for assembling by structural bonding the cross bracing to the arms. Each lug has an assembling edge configured to be assembled to one end of the cross bracing by generating self-binding with a surface of the cross bracing, an adhesive layer being applied between the assembling edge and the surface of the cross bracing, and the assembling edge of each lug has a variable thickness along its periphery and in the direction of the lug axis, the thickness being selected so as to minimize stresses exerted on the adhesive in the assembling zone. A method assembles the motor vehicle axle system.

Abstract: A semiconductor product logic chip (20) including a logic network (27-1) to be fed by a tie-up/tie down circuit (21-1). A tie-up/tie-down circuit is comprised of a non-inverting buffer book (22-1) whose input terminal (23-1) is controlled from the outside by a connection (25) to a primary input terminal (24) of the said chip. Its output terminal (26-1) is connected to said logic network. The primary input terminal is connected to a voltage supply means (29) capable of supplying a constant supply voltage VDD/GND in the SYSTEM mode and a supply voltage varying between VDD and GND, during the TEST mode. When the chip operates in the SYSTEM mode, the supply voltage means is the VDD/GND power supply, so that the primary input terminal is directly tied to the VDD/GND power supply. As a result, the tie-up/tie-down circuit generates a steady logic level "1"/"0" on its output terminal.