Abstract: A processor comprises a plurality of parallel channels having an upstream end and a downstream end, Each channel comprises a video data bus for continuously transferring video data from the upstream end to the downstream end, a plurality of modules serially connected along the video data bus and a host computer connected to the downstream end of the plurality of channels for receiving the video data. Each module comprises a crossbar switch, a pixel processing element connected to the crossbar switch, a delay resource connected across the crossbar switch and a microprocessor operably integrated within each module for controlling the operation thereof. The microprocessors of each module are serially connected together for transmitting and undertaking commands. The host computer is also connected to the microprocessor of each module for issuing commands for controlling the operation of the processor.