Abstract: A wake-up circuit and method are provided for detecting and preventing false positive wake-up events in an electronic device in a sleep mode. Methodology entails producing first, second, and third sensor signals at successive first, second, and third instants in time in response to a physical stimulus detected by a sensor of the wake-up circuit. The first sensor signal is selected to be a reference value. A first difference value is determined between the second sensor signal land the reference value, a second difference value is determined between the third sensor signal and the reference value, and communication of a wake-up signal to the electronic device is prevented when at least one of the first and second difference values fails to exceed a threshold value.

Abstract: A wake-up circuit and method are provided for detecting and preventing false positive wake-up events in an electronic device in a sleep mode. Methodology entails producing first, second, and third sensor signals at successive first, second, and third instants in time in response to a physical stimulus detected by a sensor of the wake-up circuit. The first sensor signal is selected to be a reference value. A first difference value is determined between the second sensor signal and the reference value, a second difference value is determined between the third sensor signal and the reference value, and communication of a wake-up signal to the electronic device is prevented when at least one of the first and second difference values fails to exceed a threshold value.

Abstract: A method of controlling operating parameters of a radio frequency power amplifier amplifying an input signal applied in bursts with controlled input power to an input of the power amplifier, comprising responding to gain variation parameters relating to variations in the scalar gain of said amplifier starting during an initial ramp-up period of a first burst to control supply voltage and quiescent current parameters for said amplifier during a subsequent burst.

Abstract: A wireless communication unit comprises a transmitter having a power amplifier and a feedback path operably coupled to the power amplifier. The feedback path comprises a coupler for feeding back a portion of a signal to be transmitted and a detector for detecting a power level of the fed back signal. A controller provides a ramp signal to the power amplifier that controls an amplitude characteristic of the signal to be transmitted. Averaging logic is operably coupled to the detector and arranged to average the detected power level over a first period. Comparison logic is operably coupled to the averaging logic and arranged to compare the average detected power level with a reference value. The controller is operably coupled to the comparison logic and arranged to scale a ramp signal applied to the power amplifier in response to the comparison.

Abstract: A test unit for testing the frequency characteristics of one or more components of a transmitter of modulated signals. The test unit includes a data source for generating a test pattern of data. A test unit output is connected to the data source and connectable to an input of one or more of the components, for inputting the test pattern of data to the one or more components. The test unit includes a memory in which a first predetermined data sequence and a second predetermined data sequence are stored. The data source is connected with an data input to the memory, and the data source is arranged to generating the test pattern of data including the predetermined data sequences.

Abstract: A method of controlling operating parameters of a radio frequency power amplifier amplifying an input signal applied in bursts with controlled input power to an input of the power amplifier, comprising responding to gain variation parameters relating to variations in the scalar gain of said amplifier starting during an initial ramp-up period of a first burst to control supply voltage and quiescent current parameters for said amplifier during a subsequent burst.

Abstract: A wireless communication unit comprises a transmitter having a power amplifier and a feedback path operably coupled to the power amplifier. The feedback path comprises a coupler for feeding back a portion of a signal to be transmitted and a detector for detecting a power level of the fed back signal. A controller provides a ramp signal to the power amplifier that controls an amplitude characteristic of the signal to be transmitted. Averaging logic is operably coupled to the detector and arranged to average the detected power level over a first period. Comparison logic is operably coupled to the averaging logic and arranged to compare the average detected power level with a reference value. The controller is operably coupled to the comparison logic and arranged to scale a ramp signal applied to the power amplifier in response to the comparison.

Abstract: A power amplifier module comprises a power amplifier circuit having an output power level controlled by a power supply voltage. A power supply transistor controls the power supply to the power amplifier circuit from a drive signal which is received from a drive circuit. The drive circuit generates the drive signal in response to a power level input signal, which specifically may correspond to a power ramping for a GSM cellular communication system. The power amplifier module furthermore comprises a detection circuit which determines an operating characteristic of the power supply transistor. The operating characteristic is preferably a saturation characteristic. A control circuit controls the drive signal in response to the operating characteristic. The control circuit preferably controls the drive signal such that the power supply transistor does not enter the linear region for a Field Effect Transistor and the saturated region for a bipolar transistor.

Abstract: A test unit for testing the frequency characteristics of one or more components of a transmitter of modulated signals. The test unit includes a data source for generating a test pattern of data. A test unit output is connected to the data source and connectable to an input of one or more of the components, for inputting the test pattern of data to the one or more components. The test unit includes a memory in which a first predetermined data sequence and a second predetermined data sequence are stored. The data source is connected with an data input to the memory, and the data source is arranged to generating the test pattern of data including the predetermined data sequences.

Abstract: A power amplifier module comprises a power amplifier circuit having an output power level controlled by a power supply voltage. A power supply transistor controls the power supply to the power amplifier circuit from a drive signal which is received from a drive circuit. The drive circuit generates the drive signal in response to a power level input signal, which specifically may correspond to a power ramping for a GSM cellular communication system. The power amplifier module furthermore comprises a detection circuit which determines an operating characteristic of the power supply transistor. The operating characteristic is preferably a saturation characteristic. A control circuit controls the drive signal in response to the operating characteristic. The control circuit preferably controls the drive signal such that the power supply transistor does not enter the linear region for a Field Effect Transistor and the saturated region for a bipolar transistor.

Abstract: An arrangement and method for impedance matching (e.g., for a power amplifier) comprising a first node (204a) for receiving an output current to be impedance matched; a second node (212, 214) for receiving output current from the first node; a first current conductor (202c) for carrying current from the first node to the second node; a third node (204b) for receiving output current from the second node; and a second current conductor (202d) for carrying current from said second node to said third node, whereby the first and second current conductors are closely positioned so that their inductance is the sum of their self-inductances and the negative sum of their mutual inductance.

Abstract: A radio frequency (RF) power amplification circuit including a power amplifier is provided for preventing breakdown of the power amplifier. The power amplifier includes an input for receiving RF signals and an output for providing amplified RF signals. The RF power amplification circuit also includes a bias circuit coupled to the input of the power amplifier to permit normal operation of the power amplifier when the base current is below a predetermined current threshold and to prevent normal operation of the power amplifier when the base current is above the predetermined current threshold.

Abstract: Power amplifier apparatus comprising a power amplifier (1) having a signal output, and a power control feedback loop (3, 4, 5) for controlling the output signal power relative to a first power target signal (8). A saturation control loop (6, 7) is responsive to a parameter indicative of saturation of the power amplifier (1) for adjusting the output signal power to a level at which the power amplifier means is substantially not saturated. A power target variation module (11, 15, 16) operable when the first power target signal (8) is at or close to a value corresponding to saturation of the power amplifier means (1) applies to the power control loop (3 to 7) a modified power target signal (17) corresponding to a power target higher than the first power target signal (8) and at which the power amplifier means (1) saturates.

Abstract: A radio frequency (RF) power amplification circuit including a power amplifier is provided for preventing breakdown of the power amplifier. The power amplifier includes an input for receiving RF signals and an output for providing amplified RF signals. The RF power amplification circuit also includes a bias circuit coupled to the input of the power amplifier to permit normal operation of the power amplifier when the base current is below a predetermined current threshold and to prevent normal operation of the power amplifier when the base current is above the predetermined current threshold.

Abstract: Power amplifier apparatus comprising a power amplifier (1) having a signal output, and a power control feedback loop (3, 4, 5) for controlling the output signal power relative to a first power target signal (8). A saturation control loop (6, 7) is responsive to a parameter indicative of saturation of the power amplifier (1) for adjusting the output signal power to a level at which the power amplifier means is substantially not saturated. A power target variation module (11, 15, 16) operable when the first power target signal (8) is at or close to a value corresponding to saturation of the power amplifier means (1) applies to the power control loop (3 to 7) a modified power target signal (17) corresponding to a power target higher than the first power target signal (8) and at which the power amplifier means (1) saturates.

Abstract: An arrangement and method for impedance matching (e.g., for a power amplifier) comprising a first node (204a) for receiving an output current to be impedance matched; a second node (212, 214) for receiving output current from the first node; a first current conductor (202c) for carrying current from the first node to the second node; a third node (204b) for receiving output current from the second node; and a second current conductor (202d) for carrying current from said second node to said third node, whereby the first and second current conductors are closely positioned so that their inductance is the sum of their self-inductances and the negative sum of their mutual inductance.

Abstract: A frequency modulator (50, 150) for modulating a carrier signal according to a modulation data signal to provide a modulated output signal (RFout), comprises a reference signal generator (54, 154) coupled to receive the modulation data signal for performing a low frequency modulation process and for generating a reference signal modulated according to the modulation data signal, and a main synthesizer (52, 152) coupled to receive the modulated reference signal and the modulation data signal for performing a high frequency modulation process and for providing the modulated output signal at an output. Preferably, the modulated reference signal has a first modulation gain (Kr) and the modulated output signal has a modulation gain (KV) which is substantially proportional to the first modulation gain (Kr).

Abstract: A direct modulation multi-accumulator fractional-N frequency synthesizer 1 for generating a carrier signal 150 modulated by a modulation signal 170, 121 is disclosed. The frequency synthesizer includes a Voltage Controlled Oscillator, VCO 50, having a tuning port for controlling the frequency of the signal 110 output by the VCO, a variable divider 20 and a multi-accumulator sequence generator 21 for controlling the variable divider, a reference signal generator 50, a phase detector 30 and a low pass filter 40. These elements are arranged to form a Phase Locked Loop arrangement, the directly modulated output signal of which is taken from the output of the VCO, wherein in-band modulation is performed by varying the variable divider and out-of-band modulation is performed by directly applying the modulating signal to the VCO tuning port.

Abstract: A monolithic RF amplifier circuit (10) suitable for use in the 0.8-2 GHz frequency range comprises, on-chip (12'), a gateable oscillator (24) running at about 2-5 times the amplifier input frequency or higher, coupled to a rectifier (30) and a low pass filter (34) for producing a DC signal which is fed via a bias/gain control circuit (46) to a bias/gain inputs (56, 58) of one or more amplification stages (60, 62) (e.g. GaAs FET) to provide bias therefore to ensure safe operation, and a priority control circuit (42) responsive to the bias. The priority control circuit (42) operates a power switch (18) that couples the amplification stages (60,62) to a power supply, only when bias is present on their bias/gain inputs (56,58) This protects the amplification stages (60,62) against overcurrent operation. A separate external port (68) to the bias/gain control circuit (46) adjusts the magnitude of the bias to permit amplifier gain and power output to be adjusted.