Abstract: A method for synthesizing a register transfer level (RTL) based design employs a bottom-up approach to generate a final top-level design. The top-level design is divided into a plurality of sub-modules. Each of the sub-modules is then independently synthesized using an RTL based design approach and independently adapted to conform to timing requirements produced for each of the sub-modules using time budgets that are based on the top-level timing requirements. Once the sub-modules are synthesized and pass individual timing requirements specific for those sub-modules, the sub-modules are integrated to form a top-level design. The top-level design may then be verified for timing requirements and other formal requirements.

Abstract: A method and arrangement for testing different types of external memories that can be coupled to a network interface controller. The network interface controller interprets the results of the memory test differently in accordance with the memory type. A fail state indicator is used by test controller to indicate the proper offset to add or subtract to a test address to calculate the actual failing memory location.

Abstract: An arrangement and method of performing a memory built-in self test (MBIST) on a memory loops together the registers that store the MBIST results. When an error is detected during the MBIST by an MBIST controller, the MBIST results are shifted serially through the register loop as well as off the chip performing the MBIST. Once all the MBIST results are shifted out for further analysis by a host computer, for example, the MBIST controller is in its original state at the time the error was detected as the MBIST results are back in the registers they occupied prior to the shifting out of the MBIST results off the chip.

Abstract: A method and arrangement for performing a memory built-in self test (MBIST) of an external memory and an internal memory of a network interface controller includes a series of burst write and burst read operations if an external memory is detected. The sequence of burst operations tests the back-to-back burst write, back-to-back burst write burst read, back-to-back burst read and back-to-back burst read burst write capabilities of the external memory, to thereby fully exercise the external memory. Additionally, the internal memory is tested by single write and single read accesses.

Abstract: A method for testing and verifying an integrated circuit using a bottom-up approach to generate a complete integrated circuit. The design for an integrated circuit is divided or defined into individual sub-system modules which are then tested either individually or as a combination of sub-system modules (e.g., a partially integrated circuit). Once all of the sub-system modules are tested and verified, the sub-system modules can be combined to form a complete integrated circuit which can then be tested. Each of the sub-system modules, the partially integrated circuit and the complete integrated circuit are tested and verified.

Abstract: A spare gate cell on a integrated circuit contains both a configurable logic gate and one or more inverters. Inputs of these circuits have an appearance, accessible by the automatic place-and-route tool, at the topmost metal layer on the integrated circuit, which is metal 3 or higher. The outputs of the circuit preferably are accessible up to the same metal layer. The combination of the configurable gate circuit and one or more inverters enables any one such cell to selectively implement a wide range of logic functions by making appropriate connections during fib-mill processing of the integrated circuit device. The use of interconnections at the topmost layer facilitates reconfiguring a circuit to implement desired logic and interconnection thereof into the pre-defined logic on the integrated circuit. The inventive spare gate cells provide a high degree of design flexibility, both for circuit debug operations and for implementation of enhanced logic functions.

Abstract: An improved bus bridge in a computer system for connecting a first data bus and a second data bus, said bus bridge having means for connecting said first and second buses, means for receiving an address representing a transaction on said first bus, means for decoding said address, means for claiming the transaction on said first bus corresponding to said address, and means for passing said transaction to said second bus, wherein the improvement comprises: (a) means for determining if said address decodes into one of a plurality of address ranges programmed in said bridge device; (b) means for determining a timing speed for the transaction corresponding to said address in accordance with the address range for said address; and (d) means for asserting a signal for claiming the transaction at said determined timing speed.

Abstract: A network interface device is provided with a memory controller to control data writing and reading to and from an external synchronous SRAM. An interface to the SRAM has a clock pad responsive to an internal clock signal to produce a SRAM clock sent to the SRAM as a reference clock to support access to the SRAM. The clock pad contains an inverter for inverting the internal clock signal so as to produce the SRAM clock in response to the inverted internal clock signal. As a result, read time allocated for reading data from the SRAM to the memory controller is made longer than a cycle of the internal clock signal.