Patents by Inventor Jacson Liu

Jacson Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7045435
    Abstract: The present invention relates to a shallow trench isolation method of a semiconductor wafer which fills dielectric material into shallow trenches between components on the surface of the semiconductor wafer to electrically isolate the components. This method can prevent dishing phenomenon from occurring over the surface of some wider shallow trenches when a chemical-mechanical polishing method is used to polish the surface of the dielectric material filled in each shallow trench.
    Type: Grant
    Filed: November 3, 1998
    Date of Patent: May 16, 2006
    Assignee: Mosel Vitelic Inc
    Inventor: Jacson Liu
  • Publication number: 20050191822
    Abstract: The present invention relates to a shallow trench isolation method of a semiconductor wafer. This method can prevent dishing phenomenon from occurring over the surface of some wider shallow trenches when a chemical-mechanical polishing method is used to polish the surface of the dielectric material filled in each shallow trench. The method comprises: (1) choosing the shallow trenches with widths greater than a predetermined size and generating at least one dummy in each chosen shallow trench to form a plurality of new trenches with widths less than the predetermined size; (2) covering the surface of the semiconductor wafer with dielectric material to form a dielectric layer; (3) condensing the dielectric layer; (4) polishing the surface of the dielectric layer filled in all the shallow trenches to align the surface of the dielectric material with the surface of the components on the semiconductor wafer.
    Type: Application
    Filed: May 12, 2005
    Publication date: September 1, 2005
    Inventor: Jacson Liu
  • Patent number: 6784115
    Abstract: Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer (160) that is thin in some regions, such as the cell region, and thicker in other regions (165), such as the periphery region. The method simultaneously provides a gate oxide layer with two or more thicknesses without the thickness control problems of prior art methods that use contaminant-containing photoresist with an etching step. According to a specific embodiment of the present invention, the gate oxide has a first thickness that is sufficiently thin to provide high driving capability for the semiconductor ROM device, and a second thickness that is sufficiently thick to provide high voltage reliability of the semiconductor ROM device.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: August 31, 2004
    Assignee: Mosel Vitelic, Inc.
    Inventors: Cheng-Tsung Ni, Jacson Liu, Chih-Sheng Chang, Hudy-Jong Wu
  • Patent number: 6346474
    Abstract: A process for creating a dual damascene structure without needing an etch stop is disclosed.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: February 12, 2002
    Assignee: Mosel Viteli Inc.
    Inventor: Jacson Liu
  • Patent number: 6319795
    Abstract: A process for fabricating a VLSI device comprising trench isolation regions. The trench isolation regions of a VLSI device is fabricated by a process comprising the following steps: Depositing and patterning pad layers on a substrate to form active regions separated from pad-layer-covered regions; forming side walls at each active region to cover portions of the active region other than its central portion; depositing a first oxide at the space surrounded by the side walls and the central portion of the active region; removing the side walls to form trenches at the active region; and depositing a second oxide on the substrate to fill the trenches and cover the first oxide, the second oxide and the first oxide together forming an oxide trench isolation region.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: November 20, 2001
    Assignee: Mosel Vitelic Inc.
    Inventor: Jacson Liu
  • Patent number: 6245467
    Abstract: A method for fabricating a deep trench capacitor by using a patterned mask having a specific pattern thereon is provided. The specific pattern is formed by caving at least one side thereof in. The method for fabricating a deep trench capacitor includes the steps of providing a substrate, forming a deep trench having an opening by using the patterned mask with the above-described pattern within a predetermined rectangular area on the substrate, and utilizing the deep trench to form a deep trench capacitor.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: June 12, 2001
    Assignee: Mosel Vitelic Inc.
    Inventors: Hsin-Tang Peng, Jacson Liu
  • Patent number: 6218267
    Abstract: The present invention relates to a shallow trench isolation method of a semiconductor wafer for filling dielectric material in each shallow trench between components on the surface of the semiconductor wafer to isolate the components electrically and prevent dishing when the chemical-mechanical polishing is performed on the surface of dielectric material in each shallow trench.
    Type: Grant
    Filed: November 11, 1998
    Date of Patent: April 17, 2001
    Assignee: Mosel Vitelic Inc.
    Inventor: Jacson Liu
  • Patent number: 6218275
    Abstract: A process for forming a contact structure of a semiconductor device includes the steps of (a) providing a substrate having a plurality of gates thereon and a first oxide layer formed between the gates, (b) forming a first dielectric layer on the oxide layer and the gates, (c) forming a second oxide layer on the first dielectric layer, and (d) removing a portion of the second oxide layer for forming first spacers alongside each of the gates.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: April 17, 2001
    Assignee: Mosel Vitelic, Inc.
    Inventors: Jing-Xian Huang, Jacson Liu
  • Patent number: 6146997
    Abstract: A simplified method for forming a self-aligned contact hole is disclosed. The method comprises the steps of (a) providing a semiconductor substrate having a gate electrode and a diffusion region thereon; (b) forming a conformal layer of etch barrier material overlying the substrate surface including the diffusion region and the upper surface and the sidewalls of the gate electrode; (c) forming an insulating layer overlying the barrier layer; (d) etching an opening through the insulating layer self-aligned and borderless to the diffusion region by using the barrier layer as an etch stop; and (e) anisotropically etching the barrier layer underneath the opening, thereby exposing the diffusion region and simultaneously forming a spacer of the etch barrier material on the sidewall of the gate electrode.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: November 14, 2000
    Assignee: Mosel Vitelic, Inc.
    Inventors: Jacson Liu, Jing-Xian Huang