Abstract: Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep-submicron technologies at deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor.

Abstract: Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep-submicron technologies at deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor.

Abstract: Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep-submicron technologies at deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor.

Abstract: Techniques are disclosed for enhancing performance of integrated or on-chip inductors by implementing a schema of conductive metal dummies in the design thereof. In some cases, a metal dummy schema may be disposed in a layer proximate an upper surface of the inductor. The techniques may be implemented to improve overall inductor performance while enabling area scaling effects such as shrinking of inductor-to-inductor spacing on a die and/or increasing the quantity of inductors that may be manufactured on a die. In some cases, conductive metal dummies may be disposed in a region of minimal or non-peak magnetic field relative to the inductor, orthogonal to current flow in the inductor, and/or so as to minimize their occupation of the overall area of the inductor.

Abstract: Techniques are disclosed for enhancing performance of integrated or on-chip inductors by implementing a schema of conductive metal dummies in the design thereof. In some cases, a metal dummy schema may be disposed in a layer proximate an upper surface of the inductor. The techniques may be implemented to improve overall inductor performance while enabling area scaling effects such as shrinking of inductor-to-inductor spacing on a die and/or increasing the quantity of inductors that may be manufactured on a die. In some cases, conductive metal dummies may be disposed in a region of minimal or non-peak magnetic field relative to the inductor, orthogonal to current flow in the inductor, and/or so as to minimize their occupation of the overall area of the inductor.

Abstract: Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep submicron technologies deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage different that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor.

Abstract: Embodiments of a calibration circuit for a current source which may include a first control switch, a second control switch, and a capacitor. In embodiments, the first control switch may be operable to couple the capacitor to the current source and the second control switch may be operable to couple the capacitor to a reference current source to enable the capacitor to be charged or discharged according to a first control signal provided to the first control switch and a second control signal provided to the second control switch. In embodiments, the calibration circuit may be included in a digital-to-analog (DAC) converter.

Abstract: Embodiments of a calibration circuit for a current source which may include a first control switch, a second control switch, and a capacitor. In embodiments, the first control switch may be operable to couple the capacitor to the current source and the second control switch may be operable to couple the capacitor to a reference current source to enable the capacitor to be charged or discharged according to a first control signal provided to the first control switch and a second control signal provided to the second control switch. In embodiments, the calibration circuit may be included in a digital-to-analog (DAC) converter.