Abstract: A system and methods for compiling and executing instructions with opportunistic inter-path reconvergence are provided. A processor may access instructions grouped by code blocks of a control flow graph. The processor may identify a first and second code block that share the same immediate dominator and the immediate post dominator. The processor may determine a first instruction for the first code block and a second instruction for the second code block include a common opcode. In response to the first instruction and second instructing sharing the common opcode, the processor may update the set of executable instructions by removing a first instruction from the first code block and a second instruction from the second code block. The processor may add, to the set of executable instructions, a third instruction comprising the opcode, the first operand, and the second operand.

Abstract: A graphics processing unit and methods for comping and executing instructions with opportunistic inter-path reconvergence are provided. An single instruction multiple thread (SIMT) stack of graphics processing unit may store data entries, each data entry comprising an operand mask. The operand mask may include bits corresponding to threads of a warp. The graphics processing unit core may access an instruction for an entry on the SIMT stack. Each of the threads may execute the instruction using either a first set of operands or a second set of operands depending on the corresponding bits of the operand mask.

Abstract: A graphics processing unit and methods for comping and executing instructions with opportunistic inter-path reconvergence are provided. An single instruction multiple thread (SIMT) stack of graphics processing unit may store data entries, each data entry comprising an operand mask. The operand mask may include bits corresponding to threads of a warp. The graphics processing unit core may access an instruction for an entry on the SIMT stack. Each of the threads may execute the instruction using either a first set of operands or a second set of operands depending on the corresponding bits of the operand mask.

Abstract: A graphics processing unit and methods for comping and executing instructions with opportunistic inter-path reconvergence are provided. A graphics processing unit may access computer executable instructions mapped to code blocks of a control flow for a warp. The code blocks may include an immediate dominator block and an intermediate post dominator block. The graphics processing unit may store a first thread mask associated with the first code block. The first thread mask may include a plurality of bits indicative of the active or non-active status for the threads of the warp, respectively. The graphics processing unit may a second thread mask corresponding to an intermediate code block between the immediate dominator block and intermediate post dominator block. The graphics processing unit may execute, with threads indicated as active by the first thread mask, instructions of the intermediate code block with a first operand or a second operand depending on the second thread mask.

Abstract: A graphics processing unit and methods for comping and executing instructions with opportunistic inter-path reconvergence are provided. A graphics processing unit may access computer executable instructions mapped to code blocks of a control flow for a warp. The code blocks may include an immediate dominator block and an intermediate post dominator block. The graphics processing unit may store a first thread mask associated with the first code block. The first thread mask may include a plurality of bits indicative of the active or non-active status for the threads of the warp, respectively. The graphics processing unit may a second thread mask corresponding to an intermediate code block between the immediate dominator block and intermediate post dominator block. The graphics processing unit may execute, with threads indicated as active by the first thread mask, instructions of the intermediate code block with a first operand or a second operand depending on the second thread mask.