Abstract: In one of the many embodiments disclosed herein, a method for dispatching read and write requests to a memory is disclosed which includes queuing at least one write request in a write queue and queuing an incoming read request in a read queue. The method also includes comparing the read request with at least one write request in the write queue to detect a matching write request, and if there is a matching write request, storing a write queue index of the matching write request as a first entry in an ordering queue. The method further includes dispatching the at least one write request to the memory in response to the first ordering queue entry.

Abstract: A memory interface unit for controlling a memory includes a read queue, a write queue, and an ordering circuit. The read queue stores read requests for the memory, and the write queue stores write requests for the memory. The ordering circuit is coupled to both the read queue and the write queue, and allows read and write requests to be dispatched to memory in an out-of-order manner with respect to each other to maximize performance without jeopardizing data coherency.