Abstract: A duty cycle calibration circuit includes a first signal-generating circuit, receiving a clock signal to generate a first signal and a second signal, wherein the second signal and the first signal are the inverse of each other and synchronous. The calibration circuit also includes a first transmission gate, supplying a supply voltage to an adjustment signal according to the first signal and the second signal, and a fourth transmission gate, coupling the inverse of the adjustment signal to a ground according to the first signal and the second signal.

Abstract: A duty cycle calibration circuit includes a first signal-generating circuit, receiving a clock signal to generate a first signal and a second signal, wherein the second signal and the first signal are the inverse of each other and synchronous. The calibration circuit also includes a first transmission gate, supplying a supply voltage to an adjustment signal according to the first signal and the second signal, and a fourth transmission gate, coupling the inverse of the adjustment signal to a ground according to the first signal and the second signal.

Abstract: A current source device having a current source array includes a plurality of current source units, a plurality of least significant bits, and a plurality of most significant bits. The current source units are arranged along a plurality rows and columns of a current source array. Each of the least significant bits includes a first amount of current source units is placed at the geometric center of the current source array. Each of the most significant bits includes a second amount of current source units. The second amount is the first amount multiplied by a positive integer. The two adjacent bits in the most significant bits are centrally symmetrical to the geometric center.

Abstract: A signal-generating circuit includes a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first inverter, a second inverter, and a third inverter. The first P-type transistor supplies a supply voltage to a first node according to an input signal. Both of the second P-type transistor and the first N-type transistor couple the first node to a second node according to the input signal. The second N-type transistor couples the first node to a ground according to the input signal. The first inverter is coupled to the second node to generate a first signal. The second inverter is coupled between the first node and a third node. The third inverter is coupled to the third node to generate a second signal. The second signal and the first signal are the reverse of each other and synchronous.

Abstract: A current source device having a current source array includes a plurality of current source units, a plurality of least significant bits, and a plurality of most significant bits. The current source units are arranged along a plurality rows and columns of a current source array. Each of the least significant bits includes a first amount of current source units is placed at the geometric center of the current source array. Each of the most significant bits includes a second amount of current source units. The second amount is the first amount multiplied by a positive integer. The two adjacent bits in the most significant bits are centrally symmetrical to the geometric center.

Abstract: A signal-generating circuit includes a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first inverter, a second inverter, and a third inverter. The first P-type transistor supplies a supply voltage to a first node according to an input signal. Both of the second P-type transistor and the first N-type transistor couple the first node to a second node according to the input signal. The second N-type transistor couples the first node to a ground according to the input signal. The first inverter is coupled to the second node to generate a first signal. The second inverter is coupled between the first node and a third node. The third inverter is coupled to the third node to generate a second signal. The second signal and the first signal are the reverse of each other and synchronous.

Abstract: A transistor with uniform density of poly silicon includes a gate terminal, a drain terminal, and a source terminal. The gate terminal is constructed by a plurality of separated poly silicon, such that the density of the poly silicon is uniform.