Abstract: A control circuit is described in which a single input terminal receives digital control signals and analog control signals. In accordance with the principles of the invention, the control circuit includes an automatic power down circuit to place the control circuit into a low power draw or “sleep” mode whenever predetermined conditions are present. The automatic power down circuit monitors the single input terminal and when no demand for motor operation occurs for a predetermined period of time, the automatic power down circuit operates to place the control circuit into the low power draw mode.

Abstract: A control circuit is described in which a single input terminal receives digital control signals and analog control signals. In accordance with the principles of the invention, the control circuit includes an automatic power down circuit to place the control circuit into a low power draw or “sleep” mode whenever predetermined conditions are present. The automatic power down circuit monitors the single input terminal and when no demand for motor operation occurs for a predetermined period of time, the automatic power down circuit operates to place the control circuit into the low power draw mode.

Abstract: A control circuit is described in which a single input terminal receives digital control signals and analog control signals. A circuit coupled to the single input provides a first output to indicate that a signal at said single input terminal is a digital signal and a second output indicates that a signal at said single input terminal is an analog signal.

Abstract: An amplifier (170) includes first and second depletion mode transistors (161, 162) operating in response to first and second complementary signals (VAMP+, VAMP−), respectively, which route a first current (ISTACK1) from a first supply terminal (171) to an output (169) of the amplifier. Third and fourth depletion mode transistors (163, 164) receive the first and second complementary signals to route a second current (ISTACK2) from a second supply terminal (Ground) to the output. The first and second currents are summed to produce an output signal (VAMP2).

Abstract: A semiconductor device (10) includes a protection circuit (12) that has an input (24) for activating the protection circuit in response to a sampling pulse (VENABLE) to detect a fault condition of the semiconductor device, and an output (30) for producing a control signal (VCONTROL1) when a fault condition is detected.

Abstract: A power converter circuit (23) and a method for controlling current in a transformer (16). The power converter circuit (23) includes a controller circuit (60), a duty cycle detector circuit (61), a soft start circuit (62), and a switch (63). The switch (63) controls the current in the transformer (16). The controller circuit (60) cooperates with the soft start circuit (62) to alter the duty cycle of the switch (63). During initial start-up, the switch (63) operates at a minimum duty cycle and increases towards a maximum duty cycle to prevent transformer (16) saturation and potential failure of the switch (63). In addition, the duty cycle detector circuit (61) alters the frequency at which the switch (63) turns on and off to reduce the power consumption of the power converter circuit (23).

Abstract: A trigger circuit (22) having a depletion mode ntype transistor (32) and a depletion mode p-type transistor (34) operate by having each gate thereof driven by an independent source. When both transistors are on, the depletion mode n-type transistor (32) is driven by Is1 to Vsupply and the depletion mode p-type transistor (34) is driven by Is2 to ground. When both transistors are off, a transistor (26) is switched on driving Is1 to ground, and a transistor (28) is switched on driving the gate of depletion mode p-type transistor (34) to Vsupply. A linear regulator (50) using a depletion mode transistor pair (52, 54) with their gates thereof driven by separate sources provides a low voltage operation with minimal current leakage. One depletion mode transistor (52) is an n-type, and the second depletion mode transistor (54) is a p-type transistor.

Abstract: A switching regulator (18) for use in a switching power supply (10) detects a fault condition by looking for asserted feedback signal during a timer period. If feedback is asserted during the timer period, then the switching power supply (10) is operating normally. If feedback is not asserted during the timer period, then the switching power supply is in a fault condition. One way of implementing the timer is to charge and discharge by-pass capacitor (23). The timer period is the time for the VCC voltage to drop from a maximum value to a predetermined threshold. A counter (102) can also be used as the timer. When a fault is detected, the gate drive signal from the switching regulator is disabled for a period of time before attempting auto-restart.

Abstract: A power converter circuit (23) and a method for controlling current in a transformer (16). The power converter circuit (23) includes a controller circuit (60), a duty cycle detector circuit (61), a soft start circuit (62), and a switch (63). The switch (63) controls the current in the transformer (16). The controller circuit (60) cooperates with the soft start circuit (62) to alter the duty cycle of the switch (63). During initial start-up, the switch (63) operates at a minimum duty cycle and increases towards a maximum duty cycle to prevent transformer (16) saturation and potential failure of the switch (63). In addition, the duty cycle detector circuit (61) alters the frequency at which the switch (63) turns on and off to reduce the power consumption of the power converter circuit (23).

Abstract: A semiconductor device (10) includes a protection circuit (12) that has an input (24) for activating the protection circuit in response to a sampling pulse (VENABLE) to detect a fault condition of the semiconductor device, and an output (30) for producing a control signal (VCONTROL1) when a fault condition is detected.

Abstract: A power converter circuit (23) and a method for controlling current in a transformer (16). The power converter circuit (23) includes a controller circuit (60), a duty cycle detector circuit (61), a soft start circuit (62), and a switch (63). The switch (63) controls the current in the transformer (16). The controller circuit (60) cooperates with the soft start circuit (62) to alter the duty cycle of the switch (63). During initial start-up, the switch (63) operates at a minimum duty cycle and increases towards a maximum duty cycle to prevent transformer (16) saturation and potential failure of the switch (63). In addition, the duty cycle detector circuit (61) alters the frequency at which the switch (63) turns on and off to reduce the power consumption of the power converter circuit (23).

Abstract: A trigger circuit (22) having a depletion mode n-type transistor (32) and a depletion mode p-type transistor (34) operate by having each gate thereof driven by an independent source. When both transistors are on, the depletion mode n-type transistor (32) is driven by Is1 to Vsupply and the depletion mode p-type transistor (34) is driven by Is2 to ground. When both transistors are off, a transistor (26) is switched on driving Is1 to ground, and a transistor (28) is switched on driving the gate of depletion mode p-type transistor (34) to Vsupply. A linear regulator (50) using a depletion mode transistor pair (52, 54) with their gates thereof driven by separate sources provides a low voltage operation with minimal current leakage. One depletion mode transistor (52) is an n-type, and the second depletion mode transistor (54) is a p-type transistor.

Abstract: A switching regulator (18) for use in a switching power supply (10) detects a fault condition by looking for asserted feedback signal during a timer period. If feedback is asserted during the timer period, then the switching power supply (10) is operating normally. If feedback is not asserted during the timer period, then the switching power supply is in a fault condition. One way of implementing the timer is to charge and discharge by-pass capacitor (23). The timer period is the time for the VCC voltage to drop from a maximum value to a predetermined threshold. A counter (102) can also be used as the timer. When a fault is detected, the gate drive signal from the switching regulator is disabled for a period of time before attempting auto-restart.

Abstract: A switching regulator (18) for use in a switching power supply (10) receives a feedback signal and provides a gate drive signal. The switching regulator enables the gate drive signal once at any point during a cycle of an oscillator signal by setting a first latch (74) upon receiving a non-asserted feedback signal. Setting the first latch triggers a pulse generator (78) to generate a pulse signal. The first latch is not reset until the end of the cycle of the oscillator signal. Therefore, the pulse generator can generate only one pulse per oscillator cycle. The pulse signal sets a second latch (80) that enables the gate drive signal. The switching regulator disables the gate drive signal by resetting the second latch. A power transistor (20) conducts an inductor current through the primary winding of the transformer (16) in response to the gate drive signal.

Abstract: A single input pin (48) provides multi-functional features for programming a power supply (10). By connecting the appropriate interface circuit (92, 100, or 112) to the single input pin (48), the power supply (10) is programmed for specific behaviors during power up and toggling of an on/off switch (96, 108). In one mode of operation a light emitting diode (106) in the interface circuit (100) is optically coupled to a microprocessor for signaling the closure of the on/off switch (108), allowing the microprocessor to control the power supply (10) through an opto-coupler (102). In another mode of operation, the single on/off switch (96) controls the power supply (10). In yet another mode of operation, Zener diode (118) in the interface circuit (112) controls the power supply (10) during brown-out and black-out conditions.

Abstract: A battery charging circuit device (10) includes a rectifier (16) and current controller (44) for directing current away from the battery (30). The rectifier (16) provides a current curve which is controlled by the current controller (44) so as to prevent the application of excess current to the battery (30) being charged in the circuit (10).

Abstract: An integrated power factor control circuit (12) for keeping an average AC line current sinusoidal and in phase with the line voltage. The integrated power factor control circuit (12) provides a boosted DC voltage greater than the amplitude of the line voltage. A transconductance amplifier (16) provides a boosted source and sink current when an output voltage is significantly out of regulation. The boosted source and sink current of the transconductance amplifier (16) increases the speed in which the voltage control loop can react to an output voltage change and reduces the time needed to generate the regulated voltage under startup. A comparator (17) provides a boost current at start up and senses a no-load condition during normal operation. The comparator (17) senses the no-load condition and stops switching to eliminate further output charging before an out of range condition occurs.

Abstract: A switching regulator controls the pulse width to a gate of a switching power transistor to maintain an average output voltage. An error amplifier in the regulation loop detects the difference between the actual output voltage and its desired value and maintains the proper regulation voltage at a loop node to control the pulse width to the gate of the power transistor. A quick-start circuit establishes a minimum loop regulation voltage at the loop node during power up allowing the error amplifier to begin regulating immediately thereby reducing start-up delay. The quick-start circuit is disabled after the loop node reaches the minimum loop regulation voltage. The switching regulator also monitors the output voltage by the same input pin to detect an overvoltage condition and shuts down the power switching transistor accordingly.

Abstract: A control circuit having slope compensation includes a current reference circuit for providing a reference current at an output. A resistor is coupled to the current reference circuit for varying the reference current. A current mirror circuit has a plurality of outputs, and an input which is coupled to the output of current reference circuit for receiving the reference current. A capacitor is coupled between a first one of the plurality of outputs of the current mirror circuit and a first supply voltage terminal. A charging/discharging circuit is coupled to the capacitor and to a second one of the plurality of outputs of the current mirror circuit for charging the capacitor to a first predetermined voltage at a first rate and discharging the capacitor to a second predetermined voltage at a second rate wherein the signal appearing across the capacitor is a ramp voltage signal.

Abstract: A power supply monitoring circuit for operating in a plurality of modes comprising first and second single input comparators coupled to first and second inputs, respectively, for sensing the voltage levels thereof. A reference circuit for generating a reference voltage at a first output. A programming circuit coupled to the outputs of the first and second single input comparators and being responsive to a third input for providing the selection of plurality of operation modes and for providing second and third outputs which are function of the voltage levels appearing at the first and second inputs.